162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 262306a36Sopenharmony_ci%YAML 1.2 362306a36Sopenharmony_ci--- 462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml# 562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 662306a36Sopenharmony_ci 762306a36Sopenharmony_cititle: Intel Local Advanced Programmable Interrupt Controller (LAPIC) 862306a36Sopenharmony_ci 962306a36Sopenharmony_cimaintainers: 1062306a36Sopenharmony_ci - Rahul Tanwar <rtanwar@maxlinear.com> 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_cidescription: | 1362306a36Sopenharmony_ci Intel's Advanced Programmable Interrupt Controller (APIC) is a 1462306a36Sopenharmony_ci family of interrupt controllers. The APIC is a split 1562306a36Sopenharmony_ci architecture design, with a local component (LAPIC) integrated 1662306a36Sopenharmony_ci into the processor itself and an external I/O APIC. Local APIC 1762306a36Sopenharmony_ci (lapic) receives interrupts from the processor's interrupt pins, 1862306a36Sopenharmony_ci from internal sources and from an external I/O APIC (ioapic). 1962306a36Sopenharmony_ci And it sends these to the processor core for handling. 2062306a36Sopenharmony_ci See [1] Chapter 8 for more details. 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_ci Many of the Intel's generic devices like hpet, ioapic, lapic have 2362306a36Sopenharmony_ci the ce4100 name in their compatible property names because they 2462306a36Sopenharmony_ci first appeared in CE4100 SoC. 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_ci This schema defines bindings for local APIC interrupt controller. 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ci [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ciproperties: 3162306a36Sopenharmony_ci compatible: 3262306a36Sopenharmony_ci const: intel,ce4100-lapic 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ci reg: 3562306a36Sopenharmony_ci maxItems: 1 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ci interrupt-controller: true 3862306a36Sopenharmony_ci 3962306a36Sopenharmony_ci '#interrupt-cells': 4062306a36Sopenharmony_ci const: 2 4162306a36Sopenharmony_ci 4262306a36Sopenharmony_ci intel,virtual-wire-mode: 4362306a36Sopenharmony_ci description: Intel defines a few possible interrupt delivery 4462306a36Sopenharmony_ci modes. With respect to boot/init time, mainly two interrupt 4562306a36Sopenharmony_ci delivery modes are possible. 4662306a36Sopenharmony_ci PIC Mode - Legacy external 8259 compliant PIC interrupt controller. 4762306a36Sopenharmony_ci Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode. 4862306a36Sopenharmony_ci For ACPI or MPS spec compliant systems, it is figured out by some read 4962306a36Sopenharmony_ci only bit field/s available in their respective defined data structures. 5062306a36Sopenharmony_ci For OF based systems, it is by default set to PIC mode. 5162306a36Sopenharmony_ci But if this optional boolean property is set, then the interrupt delivery 5262306a36Sopenharmony_ci mode is configured to virtual wire compatibility mode. 5362306a36Sopenharmony_ci type: boolean 5462306a36Sopenharmony_ci 5562306a36Sopenharmony_cirequired: 5662306a36Sopenharmony_ci - compatible 5762306a36Sopenharmony_ci - reg 5862306a36Sopenharmony_ci - interrupt-controller 5962306a36Sopenharmony_ci - '#interrupt-cells' 6062306a36Sopenharmony_ci 6162306a36Sopenharmony_ciadditionalProperties: false 6262306a36Sopenharmony_ci 6362306a36Sopenharmony_ciexamples: 6462306a36Sopenharmony_ci - | 6562306a36Sopenharmony_ci lapic0: interrupt-controller@fee00000 { 6662306a36Sopenharmony_ci compatible = "intel,ce4100-lapic"; 6762306a36Sopenharmony_ci reg = <0xfee00000 0x1000>; 6862306a36Sopenharmony_ci interrupt-controller; 6962306a36Sopenharmony_ci #interrupt-cells = <2>; 7062306a36Sopenharmony_ci intel,virtual-wire-mode; 7162306a36Sopenharmony_ci }; 72