162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
262306a36Sopenharmony_ci%YAML 1.2
362306a36Sopenharmony_ci---
462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml#
662306a36Sopenharmony_ci
762306a36Sopenharmony_cititle: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
862306a36Sopenharmony_ci
962306a36Sopenharmony_cimaintainers:
1062306a36Sopenharmony_ci  - Frank Li <Frank.Li@nxp.com>
1162306a36Sopenharmony_ci
1262306a36Sopenharmony_cidescription: |
1362306a36Sopenharmony_ci  The Messaging Unit module enables two processors within the SoC to
1462306a36Sopenharmony_ci  communicate and coordinate by passing messages (e.g. data, status
1562306a36Sopenharmony_ci  and control) through the MU interface. The MU also provides the ability
1662306a36Sopenharmony_ci  for one processor (A side) to signal the other processor (B side) using
1762306a36Sopenharmony_ci  interrupts.
1862306a36Sopenharmony_ci
1962306a36Sopenharmony_ci  Because the MU manages the messaging between processors, the MU uses
2062306a36Sopenharmony_ci  different clocks (from each side of the different peripheral buses).
2162306a36Sopenharmony_ci  Therefore, the MU must synchronize the accesses from one side to the
2262306a36Sopenharmony_ci  other. The MU accomplishes synchronization using two sets of matching
2362306a36Sopenharmony_ci  registers (Processor A-side, Processor B-side).
2462306a36Sopenharmony_ci
2562306a36Sopenharmony_ci  MU can work as msi interrupt controller to do doorbell
2662306a36Sopenharmony_ci
2762306a36Sopenharmony_ciallOf:
2862306a36Sopenharmony_ci  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
2962306a36Sopenharmony_ci
3062306a36Sopenharmony_ciproperties:
3162306a36Sopenharmony_ci  compatible:
3262306a36Sopenharmony_ci    enum:
3362306a36Sopenharmony_ci      - fsl,imx6sx-mu-msi
3462306a36Sopenharmony_ci      - fsl,imx7ulp-mu-msi
3562306a36Sopenharmony_ci      - fsl,imx8ulp-mu-msi
3662306a36Sopenharmony_ci      - fsl,imx8ulp-mu-msi-s4
3762306a36Sopenharmony_ci
3862306a36Sopenharmony_ci  reg:
3962306a36Sopenharmony_ci    items:
4062306a36Sopenharmony_ci      - description: a side register base address
4162306a36Sopenharmony_ci      - description: b side register base address
4262306a36Sopenharmony_ci
4362306a36Sopenharmony_ci  reg-names:
4462306a36Sopenharmony_ci    items:
4562306a36Sopenharmony_ci      - const: processor-a-side
4662306a36Sopenharmony_ci      - const: processor-b-side
4762306a36Sopenharmony_ci
4862306a36Sopenharmony_ci  interrupts:
4962306a36Sopenharmony_ci    description: a side interrupt number.
5062306a36Sopenharmony_ci    maxItems: 1
5162306a36Sopenharmony_ci
5262306a36Sopenharmony_ci  clocks:
5362306a36Sopenharmony_ci    maxItems: 1
5462306a36Sopenharmony_ci
5562306a36Sopenharmony_ci  power-domains:
5662306a36Sopenharmony_ci    items:
5762306a36Sopenharmony_ci      - description: a side power domain
5862306a36Sopenharmony_ci      - description: b side power domain
5962306a36Sopenharmony_ci
6062306a36Sopenharmony_ci  power-domain-names:
6162306a36Sopenharmony_ci    items:
6262306a36Sopenharmony_ci      - const: processor-a-side
6362306a36Sopenharmony_ci      - const: processor-b-side
6462306a36Sopenharmony_ci
6562306a36Sopenharmony_ci  interrupt-controller: true
6662306a36Sopenharmony_ci
6762306a36Sopenharmony_ci  msi-controller: true
6862306a36Sopenharmony_ci
6962306a36Sopenharmony_ci  "#msi-cells":
7062306a36Sopenharmony_ci    const: 0
7162306a36Sopenharmony_ci
7262306a36Sopenharmony_cirequired:
7362306a36Sopenharmony_ci  - compatible
7462306a36Sopenharmony_ci  - reg
7562306a36Sopenharmony_ci  - interrupts
7662306a36Sopenharmony_ci  - interrupt-controller
7762306a36Sopenharmony_ci  - msi-controller
7862306a36Sopenharmony_ci  - "#msi-cells"
7962306a36Sopenharmony_ci
8062306a36Sopenharmony_ciadditionalProperties: false
8162306a36Sopenharmony_ci
8262306a36Sopenharmony_ciexamples:
8362306a36Sopenharmony_ci  - |
8462306a36Sopenharmony_ci    #include <dt-bindings/interrupt-controller/arm-gic.h>
8562306a36Sopenharmony_ci    #include <dt-bindings/firmware/imx/rsrc.h>
8662306a36Sopenharmony_ci
8762306a36Sopenharmony_ci    msi-controller@5d270000 {
8862306a36Sopenharmony_ci        compatible = "fsl,imx6sx-mu-msi";
8962306a36Sopenharmony_ci        msi-controller;
9062306a36Sopenharmony_ci        #msi-cells = <0>;
9162306a36Sopenharmony_ci        interrupt-controller;
9262306a36Sopenharmony_ci        reg = <0x5d270000 0x10000>,     /* A side */
9362306a36Sopenharmony_ci              <0x5d300000 0x10000>;     /* B side */
9462306a36Sopenharmony_ci        reg-names = "processor-a-side", "processor-b-side";
9562306a36Sopenharmony_ci        interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
9662306a36Sopenharmony_ci        power-domains = <&pd IMX_SC_R_MU_12A>,
9762306a36Sopenharmony_ci                        <&pd IMX_SC_R_MU_12B>;
9862306a36Sopenharmony_ci        power-domain-names = "processor-a-side", "processor-b-side";
9962306a36Sopenharmony_ci    };
100