162306a36Sopenharmony_ci* ARM Nested Vector Interrupt Controller (NVIC) 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciThe NVIC provides an interrupt controller that is tightly coupled to 462306a36Sopenharmony_ciCortex-M based processor cores. The NVIC implemented on different SoCs 562306a36Sopenharmony_civary in the number of interrupts and priority bits per interrupt. 662306a36Sopenharmony_ci 762306a36Sopenharmony_ciMain node required properties: 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci- compatible : should be one of: 1062306a36Sopenharmony_ci "arm,v6m-nvic" 1162306a36Sopenharmony_ci "arm,v7m-nvic" 1262306a36Sopenharmony_ci "arm,v8m-nvic" 1362306a36Sopenharmony_ci- interrupt-controller : Identifies the node as an interrupt controller 1462306a36Sopenharmony_ci- #interrupt-cells : Specifies the number of cells needed to encode an 1562306a36Sopenharmony_ci interrupt source. The type shall be a <u32> and the value shall be 2. 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ci The 1st cell contains the interrupt number for the interrupt type. 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ci The 2nd cell is the priority of the interrupt. 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ci- reg : Specifies base physical address(s) and size of the NVIC registers. 2262306a36Sopenharmony_ci This is at a fixed address (0xe000e100) and size (0xc00). 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ci- arm,num-irq-priority-bits: The number of priority bits implemented by the 2562306a36Sopenharmony_ci given SoC 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_ciExample: 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci intc: interrupt-controller@e000e100 { 3062306a36Sopenharmony_ci compatible = "arm,v7m-nvic"; 3162306a36Sopenharmony_ci #interrupt-cells = <2>; 3262306a36Sopenharmony_ci #address-cells = <1>; 3362306a36Sopenharmony_ci interrupt-controller; 3462306a36Sopenharmony_ci reg = <0xe000e100 0xc00>; 3562306a36Sopenharmony_ci arm,num-irq-priority-bits = <4>; 3662306a36Sopenharmony_ci }; 37