162306a36Sopenharmony_ciAlpine MSIX controller
262306a36Sopenharmony_ci
362306a36Sopenharmony_ciSee arm,gic-v3.txt for SPI and MSI definitions.
462306a36Sopenharmony_ci
562306a36Sopenharmony_ciRequired properties:
662306a36Sopenharmony_ci
762306a36Sopenharmony_ci- compatible: should be "al,alpine-msix"
862306a36Sopenharmony_ci- reg: physical base address and size of the registers
962306a36Sopenharmony_ci- interrupt-controller: identifies the node as an interrupt controller
1062306a36Sopenharmony_ci- msi-controller: identifies the node as an PCI Message Signaled Interrupt
1162306a36Sopenharmony_ci		  controller
1262306a36Sopenharmony_ci- al,msi-base-spi: SPI base of the MSI frame
1362306a36Sopenharmony_ci- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
1462306a36Sopenharmony_ci
1562306a36Sopenharmony_ciExample:
1662306a36Sopenharmony_ci
1762306a36Sopenharmony_cimsix: msix {
1862306a36Sopenharmony_ci	compatible = "al,alpine-msix";
1962306a36Sopenharmony_ci	reg = <0x0 0xfbe00000 0x0 0x100000>;
2062306a36Sopenharmony_ci	interrupt-parent = <&gic>;
2162306a36Sopenharmony_ci	interrupt-controller;
2262306a36Sopenharmony_ci	msi-controller;
2362306a36Sopenharmony_ci	al,msi-base-spi = <160>;
2462306a36Sopenharmony_ci	al,msi-num-spis = <160>;
2562306a36Sopenharmony_ci};
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