162306a36Sopenharmony_ciI2C for Hisilicon hix5hd2 chipset platform
262306a36Sopenharmony_ci
362306a36Sopenharmony_ciRequired properties:
462306a36Sopenharmony_ci- compatible: Must be "hisilicon,hix5hd2-i2c"
562306a36Sopenharmony_ci- reg: physical base address of the controller and length of memory mapped
662306a36Sopenharmony_ci     region.
762306a36Sopenharmony_ci- interrupts: interrupt number to the cpu.
862306a36Sopenharmony_ci- #address-cells = <1>;
962306a36Sopenharmony_ci- #size-cells = <0>;
1062306a36Sopenharmony_ci- clocks: phandles to input clocks.
1162306a36Sopenharmony_ci
1262306a36Sopenharmony_ciOptional properties:
1362306a36Sopenharmony_ci- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
1462306a36Sopenharmony_ci- Child nodes conforming to i2c bus binding
1562306a36Sopenharmony_ci
1662306a36Sopenharmony_ciExamples:
1762306a36Sopenharmony_ciI2C0@f8b10000 {
1862306a36Sopenharmony_ci	compatible = "hisilicon,hix5hd2-i2c";
1962306a36Sopenharmony_ci	reg = <0xf8b10000 0x1000>;
2062306a36Sopenharmony_ci	interrupts = <0 38 4>;
2162306a36Sopenharmony_ci	clocks = <&clock HIX5HD2_I2C0_RST>;
2262306a36Sopenharmony_ci	#address-cells = <1>;
2362306a36Sopenharmony_ci	#size-cells = <0>;
2462306a36Sopenharmony_ci}
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