162306a36Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 262306a36Sopenharmony_ci%YAML 1.2 362306a36Sopenharmony_ci--- 462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/gpio/mediatek,mt7621-gpio.yaml# 562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 662306a36Sopenharmony_ci 762306a36Sopenharmony_cititle: Mediatek MT7621 SoC GPIO controller 862306a36Sopenharmony_ci 962306a36Sopenharmony_cimaintainers: 1062306a36Sopenharmony_ci - Sergio Paracuellos <sergio.paracuellos@gmail.com> 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_cidescription: | 1362306a36Sopenharmony_ci The IP core used inside these SoCs has 3 banks of 32 GPIOs each. 1462306a36Sopenharmony_ci The registers of all the banks are interwoven inside one single IO range. 1562306a36Sopenharmony_ci We load one GPIO controller instance per bank. Also the GPIO controller can receive 1662306a36Sopenharmony_ci interrupts on any of the GPIOs, either edge or level. It then interrupts the CPU 1762306a36Sopenharmony_ci using GIC INT12. 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ciproperties: 2062306a36Sopenharmony_ci $nodename: 2162306a36Sopenharmony_ci pattern: "^gpio@[0-9a-f]+$" 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci compatible: 2462306a36Sopenharmony_ci const: mediatek,mt7621-gpio 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_ci reg: 2762306a36Sopenharmony_ci maxItems: 1 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci "#gpio-cells": 3062306a36Sopenharmony_ci const: 2 3162306a36Sopenharmony_ci 3262306a36Sopenharmony_ci gpio-controller: true 3362306a36Sopenharmony_ci gpio-ranges: true 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci interrupt-controller: true 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ci "#interrupt-cells": 3862306a36Sopenharmony_ci const: 2 3962306a36Sopenharmony_ci 4062306a36Sopenharmony_ci interrupts: 4162306a36Sopenharmony_ci maxItems: 1 4262306a36Sopenharmony_ci 4362306a36Sopenharmony_cirequired: 4462306a36Sopenharmony_ci - compatible 4562306a36Sopenharmony_ci - reg 4662306a36Sopenharmony_ci - "#gpio-cells" 4762306a36Sopenharmony_ci - gpio-controller 4862306a36Sopenharmony_ci - gpio-ranges 4962306a36Sopenharmony_ci - interrupt-controller 5062306a36Sopenharmony_ci - "#interrupt-cells" 5162306a36Sopenharmony_ci - interrupts 5262306a36Sopenharmony_ci 5362306a36Sopenharmony_ciadditionalProperties: false 5462306a36Sopenharmony_ci 5562306a36Sopenharmony_ciexamples: 5662306a36Sopenharmony_ci - | 5762306a36Sopenharmony_ci #include <dt-bindings/gpio/gpio.h> 5862306a36Sopenharmony_ci #include <dt-bindings/interrupt-controller/mips-gic.h> 5962306a36Sopenharmony_ci 6062306a36Sopenharmony_ci gpio@600 { 6162306a36Sopenharmony_ci compatible = "mediatek,mt7621-gpio"; 6262306a36Sopenharmony_ci reg = <0x600 0x100>; 6362306a36Sopenharmony_ci #gpio-cells = <2>; 6462306a36Sopenharmony_ci gpio-controller; 6562306a36Sopenharmony_ci gpio-ranges = <&pinctrl 0 0 95>; 6662306a36Sopenharmony_ci interrupt-controller; 6762306a36Sopenharmony_ci #interrupt-cells = <2>; 6862306a36Sopenharmony_ci interrupt-parent = <&gic>; 6962306a36Sopenharmony_ci interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>; 7062306a36Sopenharmony_ci }; 7162306a36Sopenharmony_ci 7262306a36Sopenharmony_ci... 73