162306a36Sopenharmony_ci* IBM/AMCC/APM GPIO Controller for PowerPC 4XX series and compatible SoCs 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciAll GPIOs are pin-shared with other functions. DCRs control whether a 462306a36Sopenharmony_ciparticular pin that has GPIO capabilities acts as a GPIO or is used for 562306a36Sopenharmony_cianother purpose. GPIO outputs are separately programmable to emulate 662306a36Sopenharmony_cian open-drain driver. 762306a36Sopenharmony_ci 862306a36Sopenharmony_ciRequired properties: 962306a36Sopenharmony_ci - compatible: must be "ibm,ppc4xx-gpio" 1062306a36Sopenharmony_ci - reg: address and length of the register set for the device 1162306a36Sopenharmony_ci - #gpio-cells: must be set to 2. The first cell is the pin number 1262306a36Sopenharmony_ci and the second cell is used to specify the gpio polarity: 1362306a36Sopenharmony_ci 0 = active high 1462306a36Sopenharmony_ci 1 = active low 1562306a36Sopenharmony_ci - gpio-controller: marks the device node as a gpio controller. 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ciExample: 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ciGPIO0: gpio@ef600b00 { 2062306a36Sopenharmony_ci compatible = "ibm,ppc4xx-gpio"; 2162306a36Sopenharmony_ci reg = <0xef600b00 0x00000048>; 2262306a36Sopenharmony_ci #gpio-cells = <2>; 2362306a36Sopenharmony_ci gpio-controller; 2462306a36Sopenharmony_ci}; 25