162306a36Sopenharmony_ciAPM X-Gene Standby GPIO controller bindings 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciThis is a gpio controller in the standby domain. It also supports interrupt in 462306a36Sopenharmony_cisome particular pins which are sourced to its parent interrupt controller 562306a36Sopenharmony_cias diagram below: 662306a36Sopenharmony_ci +-----------------+ 762306a36Sopenharmony_ci | X-Gene standby | 862306a36Sopenharmony_ci | GPIO controller +------ GPIO_0 962306a36Sopenharmony_ci+------------+ | | ... 1062306a36Sopenharmony_ci| Parent IRQ | EXT_INT_0 | +------ GPIO_8/EXT_INT_0 1162306a36Sopenharmony_ci| controller | (SPI40) | | ... 1262306a36Sopenharmony_ci| (GICv2) +--------------+ +------ GPIO_[N+8]/EXT_INT_N 1362306a36Sopenharmony_ci| | ... | | 1462306a36Sopenharmony_ci| | EXT_INT_N | +------ GPIO_[N+9] 1562306a36Sopenharmony_ci| | (SPI[40 + N])| | ... 1662306a36Sopenharmony_ci| +--------------+ +------ GPIO_MAX 1762306a36Sopenharmony_ci+------------+ +-----------------+ 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ciRequired properties: 2062306a36Sopenharmony_ci- compatible: "apm,xgene-gpio-sb" for the X-Gene Standby GPIO controller 2162306a36Sopenharmony_ci- reg: Physical base address and size of the controller's registers 2262306a36Sopenharmony_ci- #gpio-cells: Should be two. 2362306a36Sopenharmony_ci - first cell is the pin number 2462306a36Sopenharmony_ci - second cell is used to specify the gpio polarity: 2562306a36Sopenharmony_ci 0 = active high 2662306a36Sopenharmony_ci 1 = active low 2762306a36Sopenharmony_ci- gpio-controller: Marks the device node as a GPIO controller. 2862306a36Sopenharmony_ci- interrupts: The EXT_INT_0 parent interrupt resource must be listed first. 2962306a36Sopenharmony_ci- interrupt-cells: Should be two. 3062306a36Sopenharmony_ci - first cell is 0-N corresponding for EXT_INT_0 to EXT_INT_N. 3162306a36Sopenharmony_ci - second cell is used to specify flags. 3262306a36Sopenharmony_ci- interrupt-controller: Marks the device node as an interrupt controller. 3362306a36Sopenharmony_ci- apm,nr-gpios: Optional, specify number of gpios pin. 3462306a36Sopenharmony_ci- apm,nr-irqs: Optional, specify number of interrupt pins. 3562306a36Sopenharmony_ci- apm,irq-start: Optional, specify lowest gpio pin support interrupt. 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ciExample: 3862306a36Sopenharmony_ci sbgpio: gpio@17001000{ 3962306a36Sopenharmony_ci compatible = "apm,xgene-gpio-sb"; 4062306a36Sopenharmony_ci reg = <0x0 0x17001000 0x0 0x400>; 4162306a36Sopenharmony_ci #gpio-cells = <2>; 4262306a36Sopenharmony_ci gpio-controller; 4362306a36Sopenharmony_ci interrupts = <0x0 0x28 0x1>, 4462306a36Sopenharmony_ci <0x0 0x29 0x1>, 4562306a36Sopenharmony_ci <0x0 0x2a 0x1>, 4662306a36Sopenharmony_ci <0x0 0x2b 0x1>, 4762306a36Sopenharmony_ci <0x0 0x2c 0x1>, 4862306a36Sopenharmony_ci <0x0 0x2d 0x1>; 4962306a36Sopenharmony_ci interrupt-parent = <&gic>; 5062306a36Sopenharmony_ci #interrupt-cells = <2>; 5162306a36Sopenharmony_ci interrupt-controller; 5262306a36Sopenharmony_ci apm,nr-gpios = <22>; 5362306a36Sopenharmony_ci apm,nr-irqs = <6>; 5462306a36Sopenharmony_ci apm,irq-start = <8>; 5562306a36Sopenharmony_ci }; 5662306a36Sopenharmony_ci 5762306a36Sopenharmony_ci testuser { 5862306a36Sopenharmony_ci compatible = "example,testuser"; 5962306a36Sopenharmony_ci /* Use the GPIO_13/EXT_INT_5 line as an active high triggered 6062306a36Sopenharmony_ci * level interrupt 6162306a36Sopenharmony_ci */ 6262306a36Sopenharmony_ci interrupts = <5 4>; 6362306a36Sopenharmony_ci interrupt-parent = <&sbgpio>; 6462306a36Sopenharmony_ci }; 65