162306a36Sopenharmony_ci* NVIDIA Tegra APB DMA controller
262306a36Sopenharmony_ci
362306a36Sopenharmony_ciRequired properties:
462306a36Sopenharmony_ci- compatible: Should be "nvidia,<chip>-apbdma"
562306a36Sopenharmony_ci- reg: Should contain DMA registers location and length. This should include
662306a36Sopenharmony_ci  all of the per-channel registers.
762306a36Sopenharmony_ci- interrupts: Should contain all of the per-channel DMA interrupts.
862306a36Sopenharmony_ci- clocks: Must contain one entry, for the module clock.
962306a36Sopenharmony_ci  See ../clocks/clock-bindings.txt for details.
1062306a36Sopenharmony_ci- resets : Must contain an entry for each entry in reset-names.
1162306a36Sopenharmony_ci  See ../reset/reset.txt for details.
1262306a36Sopenharmony_ci- reset-names : Must include the following entries:
1362306a36Sopenharmony_ci  - dma
1462306a36Sopenharmony_ci- #dma-cells : Must be <1>. This dictates the length of DMA specifiers in
1562306a36Sopenharmony_ci  client nodes' dmas properties. The specifier represents the DMA request
1662306a36Sopenharmony_ci  select value for the peripheral. For more details, consult the Tegra TRM's
1762306a36Sopenharmony_ci  documentation of the APB DMA channel control register REQ_SEL field.
1862306a36Sopenharmony_ci
1962306a36Sopenharmony_ciExamples:
2062306a36Sopenharmony_ci
2162306a36Sopenharmony_ciapbdma: dma@6000a000 {
2262306a36Sopenharmony_ci	compatible = "nvidia,tegra20-apbdma";
2362306a36Sopenharmony_ci	reg = <0x6000a000 0x1200>;
2462306a36Sopenharmony_ci	interrupts = < 0 136 0x04
2562306a36Sopenharmony_ci		       0 137 0x04
2662306a36Sopenharmony_ci		       0 138 0x04
2762306a36Sopenharmony_ci		       0 139 0x04
2862306a36Sopenharmony_ci		       0 140 0x04
2962306a36Sopenharmony_ci		       0 141 0x04
3062306a36Sopenharmony_ci		       0 142 0x04
3162306a36Sopenharmony_ci		       0 143 0x04
3262306a36Sopenharmony_ci		       0 144 0x04
3362306a36Sopenharmony_ci		       0 145 0x04
3462306a36Sopenharmony_ci		       0 146 0x04
3562306a36Sopenharmony_ci		       0 147 0x04
3662306a36Sopenharmony_ci		       0 148 0x04
3762306a36Sopenharmony_ci		       0 149 0x04
3862306a36Sopenharmony_ci		       0 150 0x04
3962306a36Sopenharmony_ci		       0 151 0x04 >;
4062306a36Sopenharmony_ci	clocks = <&tegra_car 34>;
4162306a36Sopenharmony_ci	resets = <&tegra_car 34>;
4262306a36Sopenharmony_ci	reset-names = "dma";
4362306a36Sopenharmony_ci	#dma-cells = <1>;
4462306a36Sopenharmony_ci};
45