162306a36Sopenharmony_ciMediaTek High-Speed DMA Controller
262306a36Sopenharmony_ci==================================
362306a36Sopenharmony_ci
462306a36Sopenharmony_ciThis device follows the generic DMA bindings defined in dma/dma.txt.
562306a36Sopenharmony_ci
662306a36Sopenharmony_ciRequired properties:
762306a36Sopenharmony_ci
862306a36Sopenharmony_ci- compatible:	Must be one of
962306a36Sopenharmony_ci		  "mediatek,mt7622-hsdma": for MT7622 SoC
1062306a36Sopenharmony_ci		  "mediatek,mt7623-hsdma": for MT7623 SoC
1162306a36Sopenharmony_ci- reg:		Should contain the register's base address and length.
1262306a36Sopenharmony_ci- interrupts:	Should contain a reference to the interrupt used by this
1362306a36Sopenharmony_ci		device.
1462306a36Sopenharmony_ci- clocks:	Should be the clock specifiers corresponding to the entry in
1562306a36Sopenharmony_ci		clock-names property.
1662306a36Sopenharmony_ci- clock-names:	Should contain "hsdma" entries.
1762306a36Sopenharmony_ci- power-domains: Phandle to the power domain that the device is part of
1862306a36Sopenharmony_ci- #dma-cells: 	The length of the DMA specifier, must be <1>. This one cell
1962306a36Sopenharmony_ci		in dmas property of a client device represents the channel
2062306a36Sopenharmony_ci		number.
2162306a36Sopenharmony_ciExample:
2262306a36Sopenharmony_ci
2362306a36Sopenharmony_ci        hsdma: dma-controller@1b007000 {
2462306a36Sopenharmony_ci		compatible = "mediatek,mt7623-hsdma";
2562306a36Sopenharmony_ci		reg = <0 0x1b007000 0 0x1000>;
2662306a36Sopenharmony_ci		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
2762306a36Sopenharmony_ci		clocks = <&ethsys CLK_ETHSYS_HSDMA>;
2862306a36Sopenharmony_ci		clock-names = "hsdma";
2962306a36Sopenharmony_ci		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
3062306a36Sopenharmony_ci		#dma-cells = <1>;
3162306a36Sopenharmony_ci	};
3262306a36Sopenharmony_ci
3362306a36Sopenharmony_ciDMA clients must use the format described in dma/dma.txt file.
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