162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
262306a36Sopenharmony_ci%YAML 1.2
362306a36Sopenharmony_ci---
462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/dma/intel,ldma.yaml#
562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml#
662306a36Sopenharmony_ci
762306a36Sopenharmony_cititle: Lightning Mountain centralized DMA controllers.
862306a36Sopenharmony_ci
962306a36Sopenharmony_cimaintainers:
1062306a36Sopenharmony_ci  - chuanhua.lei@intel.com
1162306a36Sopenharmony_ci  - mallikarjunax.reddy@intel.com
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_ciallOf:
1462306a36Sopenharmony_ci  - $ref: dma-controller.yaml#
1562306a36Sopenharmony_ci
1662306a36Sopenharmony_ciproperties:
1762306a36Sopenharmony_ci  compatible:
1862306a36Sopenharmony_ci    enum:
1962306a36Sopenharmony_ci      - intel,lgm-cdma
2062306a36Sopenharmony_ci      - intel,lgm-dma2tx
2162306a36Sopenharmony_ci      - intel,lgm-dma1rx
2262306a36Sopenharmony_ci      - intel,lgm-dma1tx
2362306a36Sopenharmony_ci      - intel,lgm-dma0tx
2462306a36Sopenharmony_ci      - intel,lgm-dma3
2562306a36Sopenharmony_ci      - intel,lgm-toe-dma30
2662306a36Sopenharmony_ci      - intel,lgm-toe-dma31
2762306a36Sopenharmony_ci
2862306a36Sopenharmony_ci  reg:
2962306a36Sopenharmony_ci    maxItems: 1
3062306a36Sopenharmony_ci
3162306a36Sopenharmony_ci  "#dma-cells":
3262306a36Sopenharmony_ci    const: 3
3362306a36Sopenharmony_ci    description:
3462306a36Sopenharmony_ci      The first cell is the peripheral's DMA request line.
3562306a36Sopenharmony_ci      The second cell is the peripheral's (port) number corresponding to the channel.
3662306a36Sopenharmony_ci      The third cell is the burst length of the channel.
3762306a36Sopenharmony_ci
3862306a36Sopenharmony_ci  dma-channels:
3962306a36Sopenharmony_ci    minimum: 1
4062306a36Sopenharmony_ci    maximum: 16
4162306a36Sopenharmony_ci
4262306a36Sopenharmony_ci  dma-channel-mask:
4362306a36Sopenharmony_ci    maxItems: 1
4462306a36Sopenharmony_ci
4562306a36Sopenharmony_ci  clocks:
4662306a36Sopenharmony_ci    maxItems: 1
4762306a36Sopenharmony_ci
4862306a36Sopenharmony_ci  resets:
4962306a36Sopenharmony_ci    maxItems: 1
5062306a36Sopenharmony_ci
5162306a36Sopenharmony_ci  reset-names:
5262306a36Sopenharmony_ci    items:
5362306a36Sopenharmony_ci      - const: ctrl
5462306a36Sopenharmony_ci
5562306a36Sopenharmony_ci  interrupts:
5662306a36Sopenharmony_ci    maxItems: 1
5762306a36Sopenharmony_ci
5862306a36Sopenharmony_ci  intel,dma-poll-cnt:
5962306a36Sopenharmony_ci    $ref: /schemas/types.yaml#/definitions/uint32
6062306a36Sopenharmony_ci    description:
6162306a36Sopenharmony_ci      DMA descriptor polling counter is used to control the poling mechanism
6262306a36Sopenharmony_ci      for the descriptor fetching for all channels.
6362306a36Sopenharmony_ci
6462306a36Sopenharmony_ci  intel,dma-byte-en:
6562306a36Sopenharmony_ci    type: boolean
6662306a36Sopenharmony_ci    description:
6762306a36Sopenharmony_ci      DMA byte enable is only valid for DMA write(RX).
6862306a36Sopenharmony_ci      Byte enable(1) means DMA write will be based on the number of dwords
6962306a36Sopenharmony_ci      instead of the whole burst.
7062306a36Sopenharmony_ci
7162306a36Sopenharmony_ci  intel,dma-drb:
7262306a36Sopenharmony_ci    type: boolean
7362306a36Sopenharmony_ci    description:
7462306a36Sopenharmony_ci      DMA descriptor read back to make sure data and desc synchronization.
7562306a36Sopenharmony_ci
7662306a36Sopenharmony_ci  intel,dma-dburst-wr:
7762306a36Sopenharmony_ci    type: boolean
7862306a36Sopenharmony_ci    description:
7962306a36Sopenharmony_ci      Enable RX dynamic burst write. When it is enabled, the DMA does RX dynamic burst;
8062306a36Sopenharmony_ci      if it is disabled, the DMA RX will still support programmable fixed burst size of 2,4,8,16.
8162306a36Sopenharmony_ci      It only applies to RX DMA and memcopy DMA.
8262306a36Sopenharmony_ci
8362306a36Sopenharmony_cirequired:
8462306a36Sopenharmony_ci  - compatible
8562306a36Sopenharmony_ci  - reg
8662306a36Sopenharmony_ci
8762306a36Sopenharmony_ciadditionalProperties: false
8862306a36Sopenharmony_ci
8962306a36Sopenharmony_ciexamples:
9062306a36Sopenharmony_ci  - |
9162306a36Sopenharmony_ci    dma0: dma-controller@e0e00000 {
9262306a36Sopenharmony_ci      compatible = "intel,lgm-cdma";
9362306a36Sopenharmony_ci      reg = <0xe0e00000 0x1000>;
9462306a36Sopenharmony_ci      #dma-cells = <3>;
9562306a36Sopenharmony_ci      dma-channels = <16>;
9662306a36Sopenharmony_ci      dma-channel-mask = <0xFFFF>;
9762306a36Sopenharmony_ci      interrupt-parent = <&ioapic1>;
9862306a36Sopenharmony_ci      interrupts = <82 1>;
9962306a36Sopenharmony_ci      resets = <&rcu0 0x30 0>;
10062306a36Sopenharmony_ci      reset-names = "ctrl";
10162306a36Sopenharmony_ci      clocks = <&cgu0 80>;
10262306a36Sopenharmony_ci      intel,dma-poll-cnt = <4>;
10362306a36Sopenharmony_ci      intel,dma-byte-en;
10462306a36Sopenharmony_ci      intel,dma-drb;
10562306a36Sopenharmony_ci    };
10662306a36Sopenharmony_ci  - |
10762306a36Sopenharmony_ci    dma3: dma-controller@ec800000 {
10862306a36Sopenharmony_ci      compatible = "intel,lgm-dma3";
10962306a36Sopenharmony_ci      reg = <0xec800000 0x1000>;
11062306a36Sopenharmony_ci      clocks = <&cgu0 71>;
11162306a36Sopenharmony_ci      resets = <&rcu0 0x10 9>;
11262306a36Sopenharmony_ci      #dma-cells = <3>;
11362306a36Sopenharmony_ci      intel,dma-poll-cnt = <16>;
11462306a36Sopenharmony_ci      intel,dma-byte-en;
11562306a36Sopenharmony_ci      intel,dma-dburst-wr;
11662306a36Sopenharmony_ci    };
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