162306a36Sopenharmony_ciTexas Instruments DRA7x Display Subsystem 262306a36Sopenharmony_ci========================================= 362306a36Sopenharmony_ci 462306a36Sopenharmony_ciSee Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic 562306a36Sopenharmony_cidescription about OMAP Display Subsystem bindings. 662306a36Sopenharmony_ci 762306a36Sopenharmony_ciDSS Core 862306a36Sopenharmony_ci-------- 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ciRequired properties: 1162306a36Sopenharmony_ci- compatible: "ti,dra7-dss" 1262306a36Sopenharmony_ci- reg: address and length of the register spaces for 'dss' 1362306a36Sopenharmony_ci- ti,hwmods: "dss_core" 1462306a36Sopenharmony_ci- clocks: handle to fclk 1562306a36Sopenharmony_ci- clock-names: "fck" 1662306a36Sopenharmony_ci- syscon: phandle to control module core syscon node 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ciOptional properties: 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_ciSome DRA7xx SoCs have one dedicated video PLL, some have two. These properties 2162306a36Sopenharmony_cican be used to describe the video PLLs: 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci- reg: address and length of the register spaces for 'pll1_clkctrl', 2462306a36Sopenharmony_ci 'pll1', 'pll2_clkctrl', 'pll2' 2562306a36Sopenharmony_ci- clocks: handle to video1 pll clock and video2 pll clock 2662306a36Sopenharmony_ci- clock-names: "video1_clk" and "video2_clk" 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ciRequired nodes: 2962306a36Sopenharmony_ci- DISPC 3062306a36Sopenharmony_ci 3162306a36Sopenharmony_ciOptional nodes: 3262306a36Sopenharmony_ci- DSS Submodules: HDMI 3362306a36Sopenharmony_ci- Video port for DPI output 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ciDPI Endpoint required properties: 3662306a36Sopenharmony_ci- data-lines: number of lines used 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_ci 3962306a36Sopenharmony_ciDISPC 4062306a36Sopenharmony_ci----- 4162306a36Sopenharmony_ci 4262306a36Sopenharmony_ciRequired properties: 4362306a36Sopenharmony_ci- compatible: "ti,dra7-dispc" 4462306a36Sopenharmony_ci- reg: address and length of the register space 4562306a36Sopenharmony_ci- ti,hwmods: "dss_dispc" 4662306a36Sopenharmony_ci- interrupts: the DISPC interrupt 4762306a36Sopenharmony_ci- clocks: handle to fclk 4862306a36Sopenharmony_ci- clock-names: "fck" 4962306a36Sopenharmony_ci 5062306a36Sopenharmony_ciOptional properties: 5162306a36Sopenharmony_ci- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit 5262306a36Sopenharmony_ci in bytes per second 5362306a36Sopenharmony_ci 5462306a36Sopenharmony_ci 5562306a36Sopenharmony_ciHDMI 5662306a36Sopenharmony_ci---- 5762306a36Sopenharmony_ci 5862306a36Sopenharmony_ciRequired properties: 5962306a36Sopenharmony_ci- compatible: "ti,dra7-hdmi" 6062306a36Sopenharmony_ci- reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy', 6162306a36Sopenharmony_ci 'core' 6262306a36Sopenharmony_ci- reg-names: "wp", "pll", "phy", "core" 6362306a36Sopenharmony_ci- interrupts: the HDMI interrupt line 6462306a36Sopenharmony_ci- ti,hwmods: "dss_hdmi" 6562306a36Sopenharmony_ci- vdda-supply: vdda power supply 6662306a36Sopenharmony_ci- clocks: handles to fclk and pll clock 6762306a36Sopenharmony_ci- clock-names: "fck", "sys_clk" 6862306a36Sopenharmony_ci 6962306a36Sopenharmony_ciOptional nodes: 7062306a36Sopenharmony_ci- Video port for HDMI output 7162306a36Sopenharmony_ci 7262306a36Sopenharmony_ciHDMI Endpoint optional properties: 7362306a36Sopenharmony_ci- lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-, 7462306a36Sopenharmony_ci D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7) 75