162306a36Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0-only
262306a36Sopenharmony_ci%YAML 1.2
362306a36Sopenharmony_ci---
462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/display/samsung/samsung,fimd.yaml#
562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml#
662306a36Sopenharmony_ci
762306a36Sopenharmony_cititle: Samsung S3C/S5P/Exynos SoC Fully Interactive Mobile Display (FIMD)
862306a36Sopenharmony_ci
962306a36Sopenharmony_cimaintainers:
1062306a36Sopenharmony_ci  - Inki Dae <inki.dae@samsung.com>
1162306a36Sopenharmony_ci  - Seung-Woo Kim <sw0312.kim@samsung.com>
1262306a36Sopenharmony_ci  - Kyungmin Park <kyungmin.park@samsung.com>
1362306a36Sopenharmony_ci  - Krzysztof Kozlowski <krzk@kernel.org>
1462306a36Sopenharmony_ci
1562306a36Sopenharmony_ciproperties:
1662306a36Sopenharmony_ci  compatible:
1762306a36Sopenharmony_ci    enum:
1862306a36Sopenharmony_ci      - samsung,s3c2443-fimd
1962306a36Sopenharmony_ci      - samsung,s3c6400-fimd
2062306a36Sopenharmony_ci      - samsung,s5pv210-fimd
2162306a36Sopenharmony_ci      - samsung,exynos3250-fimd
2262306a36Sopenharmony_ci      - samsung,exynos4210-fimd
2362306a36Sopenharmony_ci      - samsung,exynos5250-fimd
2462306a36Sopenharmony_ci      - samsung,exynos5420-fimd
2562306a36Sopenharmony_ci
2662306a36Sopenharmony_ci  '#address-cells':
2762306a36Sopenharmony_ci    const: 1
2862306a36Sopenharmony_ci
2962306a36Sopenharmony_ci  clocks:
3062306a36Sopenharmony_ci    maxItems: 2
3162306a36Sopenharmony_ci
3262306a36Sopenharmony_ci  clock-names:
3362306a36Sopenharmony_ci    items:
3462306a36Sopenharmony_ci      - const: sclk_fimd
3562306a36Sopenharmony_ci      - const: fimd
3662306a36Sopenharmony_ci
3762306a36Sopenharmony_ci  display-timings:
3862306a36Sopenharmony_ci    $ref: ../panel/display-timings.yaml#
3962306a36Sopenharmony_ci
4062306a36Sopenharmony_ci  i80-if-timings:
4162306a36Sopenharmony_ci    type: object
4262306a36Sopenharmony_ci    additionalProperties: false
4362306a36Sopenharmony_ci    description: |
4462306a36Sopenharmony_ci      Timing configuration for lcd i80 interface support.
4562306a36Sopenharmony_ci      The parameters are defined as::
4662306a36Sopenharmony_ci      VCLK(internal)  __|??????|_____|??????|_____|??????|_____|??????|_____|??
4762306a36Sopenharmony_ci                        :            :            :            :            :
4862306a36Sopenharmony_ci      Address Output  --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
4962306a36Sopenharmony_ci                        | cs-setup+1 |            :            :            :
5062306a36Sopenharmony_ci                        |<---------->|            :            :            :
5162306a36Sopenharmony_ci      Chip Select     ???????????????|____________:____________:____________|??
5262306a36Sopenharmony_ci                                     | wr-setup+1 |            | wr-hold+1  |
5362306a36Sopenharmony_ci                                     |<---------->|            |<---------->|
5462306a36Sopenharmony_ci      Write Enable    ????????????????????????????|____________|???????????????
5562306a36Sopenharmony_ci                                                  | wr-active+1|
5662306a36Sopenharmony_ci                                                  |<---------->|
5762306a36Sopenharmony_ci      Video Data      ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--
5862306a36Sopenharmony_ci
5962306a36Sopenharmony_ci    properties:
6062306a36Sopenharmony_ci      cs-setup:
6162306a36Sopenharmony_ci        $ref: /schemas/types.yaml#/definitions/uint32
6262306a36Sopenharmony_ci        description:
6362306a36Sopenharmony_ci          Clock cycles for the active period of address signal is enabled until
6462306a36Sopenharmony_ci          chip select is enabled.
6562306a36Sopenharmony_ci        default: 0
6662306a36Sopenharmony_ci
6762306a36Sopenharmony_ci      wr-active:
6862306a36Sopenharmony_ci        $ref: /schemas/types.yaml#/definitions/uint32
6962306a36Sopenharmony_ci        description:
7062306a36Sopenharmony_ci          Clock cycles for the active period of CS is enabled.
7162306a36Sopenharmony_ci        default: 1
7262306a36Sopenharmony_ci
7362306a36Sopenharmony_ci      wr-hold:
7462306a36Sopenharmony_ci        $ref: /schemas/types.yaml#/definitions/uint32
7562306a36Sopenharmony_ci        description:
7662306a36Sopenharmony_ci          Clock cycles for the active period of CS is disabled until write
7762306a36Sopenharmony_ci          signal is disabled.
7862306a36Sopenharmony_ci        default: 0
7962306a36Sopenharmony_ci
8062306a36Sopenharmony_ci      wr-setup:
8162306a36Sopenharmony_ci        $ref: /schemas/types.yaml#/definitions/uint32
8262306a36Sopenharmony_ci        description:
8362306a36Sopenharmony_ci          Clock cycles for the active period of CS signal is enabled until
8462306a36Sopenharmony_ci          write signal is enabled.
8562306a36Sopenharmony_ci        default: 0
8662306a36Sopenharmony_ci
8762306a36Sopenharmony_ci  iommus:
8862306a36Sopenharmony_ci    minItems: 1
8962306a36Sopenharmony_ci    maxItems: 2
9062306a36Sopenharmony_ci
9162306a36Sopenharmony_ci  iommu-names:
9262306a36Sopenharmony_ci    items:
9362306a36Sopenharmony_ci      - const: m0
9462306a36Sopenharmony_ci      - const: m1
9562306a36Sopenharmony_ci
9662306a36Sopenharmony_ci  interrupts:
9762306a36Sopenharmony_ci    items:
9862306a36Sopenharmony_ci      - description: FIFO level
9962306a36Sopenharmony_ci      - description: VSYNC
10062306a36Sopenharmony_ci      - description: LCD system
10162306a36Sopenharmony_ci
10262306a36Sopenharmony_ci  interrupt-names:
10362306a36Sopenharmony_ci    items:
10462306a36Sopenharmony_ci      - const: fifo
10562306a36Sopenharmony_ci      - const: vsync
10662306a36Sopenharmony_ci      - const: lcd_sys
10762306a36Sopenharmony_ci
10862306a36Sopenharmony_ci  power-domains:
10962306a36Sopenharmony_ci    maxItems: 1
11062306a36Sopenharmony_ci
11162306a36Sopenharmony_ci  reg:
11262306a36Sopenharmony_ci    maxItems: 1
11362306a36Sopenharmony_ci
11462306a36Sopenharmony_ci  samsung,invert-vden:
11562306a36Sopenharmony_ci    type: boolean
11662306a36Sopenharmony_ci    description:
11762306a36Sopenharmony_ci      Video enable signal is inverted.
11862306a36Sopenharmony_ci
11962306a36Sopenharmony_ci  samsung,invert-vclk:
12062306a36Sopenharmony_ci    type: boolean
12162306a36Sopenharmony_ci    description:
12262306a36Sopenharmony_ci      Video clock signal is inverted.
12362306a36Sopenharmony_ci
12462306a36Sopenharmony_ci  samsung,sysreg:
12562306a36Sopenharmony_ci    $ref: /schemas/types.yaml#/definitions/phandle
12662306a36Sopenharmony_ci    description:
12762306a36Sopenharmony_ci      Phandle to System Register syscon.
12862306a36Sopenharmony_ci
12962306a36Sopenharmony_ci  '#size-cells':
13062306a36Sopenharmony_ci    const: 0
13162306a36Sopenharmony_ci
13262306a36Sopenharmony_cipatternProperties:
13362306a36Sopenharmony_ci  "^port@[0-4]+$":
13462306a36Sopenharmony_ci    $ref: /schemas/graph.yaml#/properties/port
13562306a36Sopenharmony_ci    description: |
13662306a36Sopenharmony_ci      Contains ports with port with index::
13762306a36Sopenharmony_ci       0 - for CAMIF0 input,
13862306a36Sopenharmony_ci       1 - for CAMIF1 input,
13962306a36Sopenharmony_ci       2 - for CAMIF2 input,
14062306a36Sopenharmony_ci       3 - for parallel output,
14162306a36Sopenharmony_ci       4 - for write-back interface
14262306a36Sopenharmony_ci
14362306a36Sopenharmony_cirequired:
14462306a36Sopenharmony_ci  - compatible
14562306a36Sopenharmony_ci  - clocks
14662306a36Sopenharmony_ci  - clock-names
14762306a36Sopenharmony_ci  - interrupts
14862306a36Sopenharmony_ci  - interrupt-names
14962306a36Sopenharmony_ci  - reg
15062306a36Sopenharmony_ci
15162306a36Sopenharmony_ciallOf:
15262306a36Sopenharmony_ci  - if:
15362306a36Sopenharmony_ci      properties:
15462306a36Sopenharmony_ci        compatible:
15562306a36Sopenharmony_ci          contains:
15662306a36Sopenharmony_ci            const: samsung,exynos5420-fimd
15762306a36Sopenharmony_ci    then:
15862306a36Sopenharmony_ci      properties:
15962306a36Sopenharmony_ci        iommus:
16062306a36Sopenharmony_ci          minItems: 2
16162306a36Sopenharmony_ci          maxItems: 2
16262306a36Sopenharmony_ci
16362306a36Sopenharmony_ciadditionalProperties: false
16462306a36Sopenharmony_ci
16562306a36Sopenharmony_ciexamples:
16662306a36Sopenharmony_ci  - |
16762306a36Sopenharmony_ci    #include <dt-bindings/clock/exynos4.h>
16862306a36Sopenharmony_ci
16962306a36Sopenharmony_ci    fimd@11c00000 {
17062306a36Sopenharmony_ci        compatible = "samsung,exynos4210-fimd";
17162306a36Sopenharmony_ci        interrupt-parent = <&combiner>;
17262306a36Sopenharmony_ci        reg = <0x11c00000 0x20000>;
17362306a36Sopenharmony_ci        interrupt-names = "fifo", "vsync", "lcd_sys";
17462306a36Sopenharmony_ci        interrupts = <11 0>, <11 1>, <11 2>;
17562306a36Sopenharmony_ci        clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
17662306a36Sopenharmony_ci        clock-names = "sclk_fimd", "fimd";
17762306a36Sopenharmony_ci        power-domains = <&pd_lcd0>;
17862306a36Sopenharmony_ci        iommus = <&sysmmu_fimd0>;
17962306a36Sopenharmony_ci        samsung,sysreg = <&sys_reg>;
18062306a36Sopenharmony_ci
18162306a36Sopenharmony_ci        #address-cells = <1>;
18262306a36Sopenharmony_ci        #size-cells = <0>;
18362306a36Sopenharmony_ci
18462306a36Sopenharmony_ci        samsung,invert-vden;
18562306a36Sopenharmony_ci        samsung,invert-vclk;
18662306a36Sopenharmony_ci
18762306a36Sopenharmony_ci        pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
18862306a36Sopenharmony_ci        pinctrl-names = "default";
18962306a36Sopenharmony_ci
19062306a36Sopenharmony_ci        port@3 {
19162306a36Sopenharmony_ci            reg = <3>;
19262306a36Sopenharmony_ci
19362306a36Sopenharmony_ci            fimd_dpi_ep: endpoint {
19462306a36Sopenharmony_ci                remote-endpoint = <&lcd_ep>;
19562306a36Sopenharmony_ci            };
19662306a36Sopenharmony_ci        };
19762306a36Sopenharmony_ci    };
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