162306a36Sopenharmony_ciRockchip RK3399 specific extensions to the cdn Display Port 262306a36Sopenharmony_ci================================ 362306a36Sopenharmony_ci 462306a36Sopenharmony_ciRequired properties: 562306a36Sopenharmony_ci- compatible: must be "rockchip,rk3399-cdn-dp" 662306a36Sopenharmony_ci 762306a36Sopenharmony_ci- reg: physical base address of the controller and length 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci- clocks: from common clock binding: handle to dp clock. 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci- clock-names: from common clock binding: 1262306a36Sopenharmony_ci Required elements: "core-clk" "pclk" "spdif" "grf" 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci- resets : a list of phandle + reset specifier pairs 1562306a36Sopenharmony_ci- reset-names : string of reset names 1662306a36Sopenharmony_ci Required elements: "apb", "core", "dptx", "spdif" 1762306a36Sopenharmony_ci- power-domains : power-domain property defined with a phandle 1862306a36Sopenharmony_ci to respective power domain. 1962306a36Sopenharmony_ci- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE> 2062306a36Sopenharmony_ci- assigned-clock-rates : the DP core clk frequency, shall be: 100000000 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_ci- rockchip,grf: this soc should set GRF regs, so need get grf here. 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ci- ports: contain a port nodes with endpoint definitions as defined in 2562306a36Sopenharmony_ci Documentation/devicetree/bindings/media/video-interfaces.txt. 2662306a36Sopenharmony_ci contained 2 endpoints, connecting to the output of vop. 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ci- phys: from general PHY binding: the phandle for the PHY device. 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ci- extcon: extcon specifier for the Power Delivery 3162306a36Sopenharmony_ci 3262306a36Sopenharmony_ci- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ci------------------------------------------------------------------------------- 3562306a36Sopenharmony_ci 3662306a36Sopenharmony_ciExample: 3762306a36Sopenharmony_ci cdn_dp: dp@fec00000 { 3862306a36Sopenharmony_ci compatible = "rockchip,rk3399-cdn-dp"; 3962306a36Sopenharmony_ci reg = <0x0 0xfec00000 0x0 0x100000>; 4062306a36Sopenharmony_ci interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4162306a36Sopenharmony_ci clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 4262306a36Sopenharmony_ci <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 4362306a36Sopenharmony_ci clock-names = "core-clk", "pclk", "spdif", "grf"; 4462306a36Sopenharmony_ci assigned-clocks = <&cru SCLK_DP_CORE>; 4562306a36Sopenharmony_ci assigned-clock-rates = <100000000>; 4662306a36Sopenharmony_ci power-domains = <&power RK3399_PD_HDCP>; 4762306a36Sopenharmony_ci phys = <&tcphy0_dp>, <&tcphy1_dp>; 4862306a36Sopenharmony_ci resets = <&cru SRST_DPTX_SPDIF_REC>; 4962306a36Sopenharmony_ci reset-names = "spdif"; 5062306a36Sopenharmony_ci extcon = <&fusb0>, <&fusb1>; 5162306a36Sopenharmony_ci rockchip,grf = <&grf>; 5262306a36Sopenharmony_ci #address-cells = <1>; 5362306a36Sopenharmony_ci #size-cells = <0>; 5462306a36Sopenharmony_ci #sound-dai-cells = <1>; 5562306a36Sopenharmony_ci 5662306a36Sopenharmony_ci ports { 5762306a36Sopenharmony_ci #address-cells = <1>; 5862306a36Sopenharmony_ci #size-cells = <0>; 5962306a36Sopenharmony_ci 6062306a36Sopenharmony_ci dp_in: port { 6162306a36Sopenharmony_ci #address-cells = <1>; 6262306a36Sopenharmony_ci #size-cells = <0>; 6362306a36Sopenharmony_ci dp_in_vopb: endpoint@0 { 6462306a36Sopenharmony_ci reg = <0>; 6562306a36Sopenharmony_ci remote-endpoint = <&vopb_out_dp>; 6662306a36Sopenharmony_ci }; 6762306a36Sopenharmony_ci 6862306a36Sopenharmony_ci dp_in_vopl: endpoint@1 { 6962306a36Sopenharmony_ci reg = <1>; 7062306a36Sopenharmony_ci remote-endpoint = <&vopl_out_dp>; 7162306a36Sopenharmony_ci }; 7262306a36Sopenharmony_ci }; 7362306a36Sopenharmony_ci }; 7462306a36Sopenharmony_ci }; 75