162306a36Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
262306a36Sopenharmony_ci%YAML 1.2
362306a36Sopenharmony_ci---
462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-mdss.yaml#
562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml#
662306a36Sopenharmony_ci
762306a36Sopenharmony_cititle: Qualcomm SC8280XP Mobile Display Subsystem
862306a36Sopenharmony_ci
962306a36Sopenharmony_cimaintainers:
1062306a36Sopenharmony_ci  - Bjorn Andersson <andersson@kernel.org>
1162306a36Sopenharmony_ci
1262306a36Sopenharmony_cidescription:
1362306a36Sopenharmony_ci  Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
1462306a36Sopenharmony_ci  sub-blocks like DPU display controller, DSI and DP interfaces etc.
1562306a36Sopenharmony_ci
1662306a36Sopenharmony_ci$ref: /schemas/display/msm/mdss-common.yaml#
1762306a36Sopenharmony_ci
1862306a36Sopenharmony_ciproperties:
1962306a36Sopenharmony_ci  compatible:
2062306a36Sopenharmony_ci    const: qcom,sc8280xp-mdss
2162306a36Sopenharmony_ci
2262306a36Sopenharmony_ci  clocks:
2362306a36Sopenharmony_ci    items:
2462306a36Sopenharmony_ci      - description: Display AHB clock from gcc
2562306a36Sopenharmony_ci      - description: Display AHB clock from dispcc
2662306a36Sopenharmony_ci      - description: Display core clock
2762306a36Sopenharmony_ci
2862306a36Sopenharmony_ci  clock-names:
2962306a36Sopenharmony_ci    items:
3062306a36Sopenharmony_ci      - const: iface
3162306a36Sopenharmony_ci      - const: ahb
3262306a36Sopenharmony_ci      - const: core
3362306a36Sopenharmony_ci
3462306a36Sopenharmony_cipatternProperties:
3562306a36Sopenharmony_ci  "^display-controller@[0-9a-f]+$":
3662306a36Sopenharmony_ci    type: object
3762306a36Sopenharmony_ci    properties:
3862306a36Sopenharmony_ci      compatible:
3962306a36Sopenharmony_ci        const: qcom,sc8280xp-dpu
4062306a36Sopenharmony_ci
4162306a36Sopenharmony_ci  "^displayport-controller@[0-9a-f]+$":
4262306a36Sopenharmony_ci    type: object
4362306a36Sopenharmony_ci    properties:
4462306a36Sopenharmony_ci      compatible:
4562306a36Sopenharmony_ci        enum:
4662306a36Sopenharmony_ci          - qcom,sc8280xp-dp
4762306a36Sopenharmony_ci          - qcom,sc8280xp-edp
4862306a36Sopenharmony_ci
4962306a36Sopenharmony_ciunevaluatedProperties: false
5062306a36Sopenharmony_ci
5162306a36Sopenharmony_ciexamples:
5262306a36Sopenharmony_ci  - |
5362306a36Sopenharmony_ci    #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
5462306a36Sopenharmony_ci    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
5562306a36Sopenharmony_ci    #include <dt-bindings/interrupt-controller/arm-gic.h>
5662306a36Sopenharmony_ci    #include <dt-bindings/interconnect/qcom,sc8280xp.h>
5762306a36Sopenharmony_ci    #include <dt-bindings/power/qcom-rpmpd.h>
5862306a36Sopenharmony_ci
5962306a36Sopenharmony_ci    display-subsystem@ae00000 {
6062306a36Sopenharmony_ci        compatible = "qcom,sc8280xp-mdss";
6162306a36Sopenharmony_ci        reg = <0x0ae00000 0x1000>;
6262306a36Sopenharmony_ci        reg-names = "mdss";
6362306a36Sopenharmony_ci
6462306a36Sopenharmony_ci        power-domains = <&dispcc0 MDSS_GDSC>;
6562306a36Sopenharmony_ci
6662306a36Sopenharmony_ci        clocks = <&gcc GCC_DISP_AHB_CLK>,
6762306a36Sopenharmony_ci                 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
6862306a36Sopenharmony_ci                 <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
6962306a36Sopenharmony_ci        clock-names = "iface",
7062306a36Sopenharmony_ci                      "ahb",
7162306a36Sopenharmony_ci                      "core";
7262306a36Sopenharmony_ci
7362306a36Sopenharmony_ci        resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
7462306a36Sopenharmony_ci
7562306a36Sopenharmony_ci        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
7662306a36Sopenharmony_ci        interrupt-controller;
7762306a36Sopenharmony_ci        #interrupt-cells = <1>;
7862306a36Sopenharmony_ci
7962306a36Sopenharmony_ci        interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
8062306a36Sopenharmony_ci                        <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
8162306a36Sopenharmony_ci        interconnect-names = "mdp0-mem", "mdp1-mem";
8262306a36Sopenharmony_ci
8362306a36Sopenharmony_ci        iommus = <&apps_smmu 0x1000 0x402>;
8462306a36Sopenharmony_ci
8562306a36Sopenharmony_ci        #address-cells = <1>;
8662306a36Sopenharmony_ci        #size-cells = <1>;
8762306a36Sopenharmony_ci        ranges;
8862306a36Sopenharmony_ci
8962306a36Sopenharmony_ci        display-controller@ae01000 {
9062306a36Sopenharmony_ci            compatible = "qcom,sc8280xp-dpu";
9162306a36Sopenharmony_ci            reg = <0x0ae01000 0x8f000>,
9262306a36Sopenharmony_ci            <0x0aeb0000 0x2008>;
9362306a36Sopenharmony_ci            reg-names = "mdp", "vbif";
9462306a36Sopenharmony_ci
9562306a36Sopenharmony_ci            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
9662306a36Sopenharmony_ci                     <&gcc GCC_DISP_SF_AXI_CLK>,
9762306a36Sopenharmony_ci                     <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
9862306a36Sopenharmony_ci                     <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
9962306a36Sopenharmony_ci                     <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
10062306a36Sopenharmony_ci                     <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
10162306a36Sopenharmony_ci            clock-names = "bus",
10262306a36Sopenharmony_ci                          "nrt_bus",
10362306a36Sopenharmony_ci                          "iface",
10462306a36Sopenharmony_ci                          "lut",
10562306a36Sopenharmony_ci                          "core",
10662306a36Sopenharmony_ci                          "vsync";
10762306a36Sopenharmony_ci
10862306a36Sopenharmony_ci            assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
10962306a36Sopenharmony_ci            assigned-clock-rates = <19200000>;
11062306a36Sopenharmony_ci
11162306a36Sopenharmony_ci            operating-points-v2 = <&mdss0_mdp_opp_table>;
11262306a36Sopenharmony_ci            power-domains = <&rpmhpd SC8280XP_MMCX>;
11362306a36Sopenharmony_ci
11462306a36Sopenharmony_ci            interrupt-parent = <&mdss0>;
11562306a36Sopenharmony_ci            interrupts = <0>;
11662306a36Sopenharmony_ci
11762306a36Sopenharmony_ci            ports {
11862306a36Sopenharmony_ci                #address-cells = <1>;
11962306a36Sopenharmony_ci                #size-cells = <0>;
12062306a36Sopenharmony_ci
12162306a36Sopenharmony_ci                port@0 {
12262306a36Sopenharmony_ci                    reg = <0>;
12362306a36Sopenharmony_ci                    endpoint {
12462306a36Sopenharmony_ci                        remote-endpoint = <&mdss0_dp0_in>;
12562306a36Sopenharmony_ci                    };
12662306a36Sopenharmony_ci                };
12762306a36Sopenharmony_ci
12862306a36Sopenharmony_ci                port@4 {
12962306a36Sopenharmony_ci                    reg = <4>;
13062306a36Sopenharmony_ci                    endpoint {
13162306a36Sopenharmony_ci                        remote-endpoint = <&mdss0_dp1_in>;
13262306a36Sopenharmony_ci                    };
13362306a36Sopenharmony_ci                };
13462306a36Sopenharmony_ci
13562306a36Sopenharmony_ci                port@5 {
13662306a36Sopenharmony_ci                    reg = <5>;
13762306a36Sopenharmony_ci                    endpoint {
13862306a36Sopenharmony_ci                        remote-endpoint = <&mdss0_dp3_in>;
13962306a36Sopenharmony_ci                    };
14062306a36Sopenharmony_ci                };
14162306a36Sopenharmony_ci
14262306a36Sopenharmony_ci                port@6 {
14362306a36Sopenharmony_ci                    reg = <6>;
14462306a36Sopenharmony_ci                    endpoint {
14562306a36Sopenharmony_ci                        remote-endpoint = <&mdss0_dp2_in>;
14662306a36Sopenharmony_ci                    };
14762306a36Sopenharmony_ci                };
14862306a36Sopenharmony_ci            };
14962306a36Sopenharmony_ci        };
15062306a36Sopenharmony_ci    };
15162306a36Sopenharmony_ci...
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