162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 262306a36Sopenharmony_ci%YAML 1.2 362306a36Sopenharmony_ci--- 462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/display/bridge/thine,thc63lvd1024.yaml# 562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 662306a36Sopenharmony_ci 762306a36Sopenharmony_cititle: Thine Electronics THC63LVD1024 LVDS Decoder 862306a36Sopenharmony_ci 962306a36Sopenharmony_cimaintainers: 1062306a36Sopenharmony_ci - Jacopo Mondi <jacopo+renesas@jmondi.org> 1162306a36Sopenharmony_ci - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_cidescription: | 1462306a36Sopenharmony_ci The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS 1562306a36Sopenharmony_ci streams to parallel data outputs. The chip supports single/dual input/output 1662306a36Sopenharmony_ci modes, handling up to two LVDS input streams and up to two digital CMOS/TTL 1762306a36Sopenharmony_ci outputs. 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ci Single or dual operation mode, output data mapping and DDR output modes are 2062306a36Sopenharmony_ci configured through input signals and the chip does not expose any control 2162306a36Sopenharmony_ci bus. 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ciproperties: 2462306a36Sopenharmony_ci compatible: 2562306a36Sopenharmony_ci const: thine,thc63lvd1024 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_ci ports: 2862306a36Sopenharmony_ci $ref: /schemas/graph.yaml#/properties/ports 2962306a36Sopenharmony_ci description: | 3062306a36Sopenharmony_ci The device can operate in single or dual input and output modes. 3162306a36Sopenharmony_ci 3262306a36Sopenharmony_ci When operating in single input mode, all pixels are received on port@0, 3362306a36Sopenharmony_ci and port@1 shall not contain any endpoint. In dual input mode, 3462306a36Sopenharmony_ci even-numbered pixels are received on port@0 and odd-numbered pixels on 3562306a36Sopenharmony_ci port@1, and both port@0 and port@1 shall contain endpoints. 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ci When operating in single output mode all pixels are output from the first 3862306a36Sopenharmony_ci CMOS/TTL port and port@3 shall not contain any endpoint. In dual output 3962306a36Sopenharmony_ci mode pixels are output from both CMOS/TTL ports and both port@2 and 4062306a36Sopenharmony_ci port@3 shall contain endpoints. 4162306a36Sopenharmony_ci 4262306a36Sopenharmony_ci properties: 4362306a36Sopenharmony_ci port@0: 4462306a36Sopenharmony_ci $ref: /schemas/graph.yaml#/properties/port 4562306a36Sopenharmony_ci description: First LVDS input port 4662306a36Sopenharmony_ci 4762306a36Sopenharmony_ci port@1: 4862306a36Sopenharmony_ci $ref: /schemas/graph.yaml#/properties/port 4962306a36Sopenharmony_ci description: Second LVDS input port 5062306a36Sopenharmony_ci 5162306a36Sopenharmony_ci port@2: 5262306a36Sopenharmony_ci $ref: /schemas/graph.yaml#/properties/port 5362306a36Sopenharmony_ci description: First digital CMOS/TTL parallel output 5462306a36Sopenharmony_ci 5562306a36Sopenharmony_ci port@3: 5662306a36Sopenharmony_ci $ref: /schemas/graph.yaml#/properties/port 5762306a36Sopenharmony_ci description: Second digital CMOS/TTL parallel output 5862306a36Sopenharmony_ci 5962306a36Sopenharmony_ci required: 6062306a36Sopenharmony_ci - port@0 6162306a36Sopenharmony_ci - port@2 6262306a36Sopenharmony_ci 6362306a36Sopenharmony_ci oe-gpios: 6462306a36Sopenharmony_ci maxItems: 1 6562306a36Sopenharmony_ci description: Output enable GPIO signal, pin name "OE", active high. 6662306a36Sopenharmony_ci 6762306a36Sopenharmony_ci powerdown-gpios: 6862306a36Sopenharmony_ci maxItems: 1 6962306a36Sopenharmony_ci description: Power down GPIO signal, pin name "/PDWN", active low. 7062306a36Sopenharmony_ci 7162306a36Sopenharmony_ci vcc-supply: 7262306a36Sopenharmony_ci description: 7362306a36Sopenharmony_ci Power supply for the TTL output, TTL CLOCKOUT signal, LVDS input, PLL and 7462306a36Sopenharmony_ci digital circuitry. 7562306a36Sopenharmony_ci 7662306a36Sopenharmony_cirequired: 7762306a36Sopenharmony_ci - compatible 7862306a36Sopenharmony_ci - ports 7962306a36Sopenharmony_ci - vcc-supply 8062306a36Sopenharmony_ci 8162306a36Sopenharmony_ciadditionalProperties: false 8262306a36Sopenharmony_ci 8362306a36Sopenharmony_ciexamples: 8462306a36Sopenharmony_ci - | 8562306a36Sopenharmony_ci #include <dt-bindings/gpio/gpio.h> 8662306a36Sopenharmony_ci 8762306a36Sopenharmony_ci lvds-decoder { 8862306a36Sopenharmony_ci compatible = "thine,thc63lvd1024"; 8962306a36Sopenharmony_ci 9062306a36Sopenharmony_ci vcc-supply = <®_lvds_vcc>; 9162306a36Sopenharmony_ci powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; 9262306a36Sopenharmony_ci 9362306a36Sopenharmony_ci ports { 9462306a36Sopenharmony_ci #address-cells = <1>; 9562306a36Sopenharmony_ci #size-cells = <0>; 9662306a36Sopenharmony_ci 9762306a36Sopenharmony_ci port@0 { 9862306a36Sopenharmony_ci reg = <0>; 9962306a36Sopenharmony_ci 10062306a36Sopenharmony_ci lvds_dec_in_0: endpoint { 10162306a36Sopenharmony_ci remote-endpoint = <&lvds_out>; 10262306a36Sopenharmony_ci }; 10362306a36Sopenharmony_ci }; 10462306a36Sopenharmony_ci 10562306a36Sopenharmony_ci port@2 { 10662306a36Sopenharmony_ci reg = <2>; 10762306a36Sopenharmony_ci 10862306a36Sopenharmony_ci lvds_dec_out_2: endpoint { 10962306a36Sopenharmony_ci remote-endpoint = <&adv7511_in>; 11062306a36Sopenharmony_ci }; 11162306a36Sopenharmony_ci }; 11262306a36Sopenharmony_ci }; 11362306a36Sopenharmony_ci }; 11462306a36Sopenharmony_ci 11562306a36Sopenharmony_ci... 116