162306a36Sopenharmony_ciMediaTek cryptographic accelerators
262306a36Sopenharmony_ci
362306a36Sopenharmony_ciRequired properties:
462306a36Sopenharmony_ci- compatible: Should be "mediatek,eip97-crypto"
562306a36Sopenharmony_ci- reg: Address and length of the register set for the device
662306a36Sopenharmony_ci- interrupts: Should contain the five crypto engines interrupts in numeric
762306a36Sopenharmony_ci	order. These are global system and four descriptor rings.
862306a36Sopenharmony_ci- clocks: the clock used by the core
962306a36Sopenharmony_ci- clock-names: Must contain "cryp".
1062306a36Sopenharmony_ci- power-domains: Must contain a reference to the PM domain.
1162306a36Sopenharmony_ci
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_ciExample:
1462306a36Sopenharmony_ci	crypto: crypto@1b240000 {
1562306a36Sopenharmony_ci		compatible = "mediatek,eip97-crypto";
1662306a36Sopenharmony_ci		reg = <0 0x1b240000 0 0x20000>;
1762306a36Sopenharmony_ci		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
1862306a36Sopenharmony_ci			     <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
1962306a36Sopenharmony_ci			     <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
2062306a36Sopenharmony_ci			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
2162306a36Sopenharmony_ci			     <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
2262306a36Sopenharmony_ci		clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
2362306a36Sopenharmony_ci		clock-names = "cryp";
2462306a36Sopenharmony_ci		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
2562306a36Sopenharmony_ci	};
26