162306a36Sopenharmony_ciBinding for NVIDIA Tegra20 CPUFreq 262306a36Sopenharmony_ci================================== 362306a36Sopenharmony_ci 462306a36Sopenharmony_ciRequired properties: 562306a36Sopenharmony_ci- clocks: Must contain an entry for the CPU clock. 662306a36Sopenharmony_ci See ../clocks/clock-bindings.txt for details. 762306a36Sopenharmony_ci- operating-points-v2: See ../bindings/opp/opp-v2.yaml for details. 862306a36Sopenharmony_ci- #cooling-cells: Should be 2. See ../thermal/thermal-cooling-devices.yaml for details. 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ciFor each opp entry in 'operating-points-v2' table: 1162306a36Sopenharmony_ci- opp-supported-hw: Two bitfields indicating: 1262306a36Sopenharmony_ci On Tegra20: 1362306a36Sopenharmony_ci 1. CPU process ID mask 1462306a36Sopenharmony_ci 2. SoC speedo ID mask 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci On Tegra30: 1762306a36Sopenharmony_ci 1. CPU process ID mask 1862306a36Sopenharmony_ci 2. CPU speedo ID mask 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_ci A bitwise AND is performed against these values and if any bit 2162306a36Sopenharmony_ci matches, the OPP gets enabled. 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci- opp-microvolt: CPU voltage triplet. 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ciOptional properties: 2662306a36Sopenharmony_ci- cpu-supply: Phandle to the CPU power supply. 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ciExample: 2962306a36Sopenharmony_ci regulators { 3062306a36Sopenharmony_ci cpu_reg: regulator0 { 3162306a36Sopenharmony_ci regulator-name = "vdd_cpu"; 3262306a36Sopenharmony_ci }; 3362306a36Sopenharmony_ci }; 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci cpu0_opp_table: opp_table0 { 3662306a36Sopenharmony_ci compatible = "operating-points-v2"; 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_ci opp@456000000 { 3962306a36Sopenharmony_ci clock-latency-ns = <125000>; 4062306a36Sopenharmony_ci opp-microvolt = <825000 825000 1125000>; 4162306a36Sopenharmony_ci opp-supported-hw = <0x03 0x0001>; 4262306a36Sopenharmony_ci opp-hz = /bits/ 64 <456000000>; 4362306a36Sopenharmony_ci }; 4462306a36Sopenharmony_ci 4562306a36Sopenharmony_ci ... 4662306a36Sopenharmony_ci }; 4762306a36Sopenharmony_ci 4862306a36Sopenharmony_ci cpus { 4962306a36Sopenharmony_ci cpu@0 { 5062306a36Sopenharmony_ci compatible = "arm,cortex-a9"; 5162306a36Sopenharmony_ci clocks = <&tegra_car TEGRA20_CLK_CCLK>; 5262306a36Sopenharmony_ci operating-points-v2 = <&cpu0_opp_table>; 5362306a36Sopenharmony_ci cpu-supply = <&cpu_reg>; 5462306a36Sopenharmony_ci #cooling-cells = <2>; 5562306a36Sopenharmony_ci }; 5662306a36Sopenharmony_ci }; 57