162306a36Sopenharmony_ciGeneric cpufreq driver 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciIt is a generic DT based cpufreq driver for frequency management. It supports 462306a36Sopenharmony_ciboth uniprocessor (UP) and symmetric multiprocessor (SMP) systems which share 562306a36Sopenharmony_ciclock and voltage across all CPUs. 662306a36Sopenharmony_ci 762306a36Sopenharmony_ciBoth required and optional properties listed below must be defined 862306a36Sopenharmony_ciunder node /cpus/cpu@0. 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ciRequired properties: 1162306a36Sopenharmony_ci- None 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ciOptional properties: 1462306a36Sopenharmony_ci- operating-points: Refer to Documentation/devicetree/bindings/opp/opp-v1.yaml for 1562306a36Sopenharmony_ci details. OPPs *must* be supplied either via DT, i.e. this property, or 1662306a36Sopenharmony_ci populated at runtime. 1762306a36Sopenharmony_ci- clock-latency: Specify the possible maximum transition latency for clock, 1862306a36Sopenharmony_ci in unit of nanoseconds. 1962306a36Sopenharmony_ci- voltage-tolerance: Specify the CPU voltage tolerance in percentage. 2062306a36Sopenharmony_ci- #cooling-cells: 2162306a36Sopenharmony_ci Please refer to 2262306a36Sopenharmony_ci Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml. 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ciExamples: 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_cicpus { 2762306a36Sopenharmony_ci #address-cells = <1>; 2862306a36Sopenharmony_ci #size-cells = <0>; 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ci cpu@0 { 3162306a36Sopenharmony_ci compatible = "arm,cortex-a9"; 3262306a36Sopenharmony_ci reg = <0>; 3362306a36Sopenharmony_ci next-level-cache = <&L2>; 3462306a36Sopenharmony_ci operating-points = < 3562306a36Sopenharmony_ci /* kHz uV */ 3662306a36Sopenharmony_ci 792000 1100000 3762306a36Sopenharmony_ci 396000 950000 3862306a36Sopenharmony_ci 198000 850000 3962306a36Sopenharmony_ci >; 4062306a36Sopenharmony_ci clock-latency = <61036>; /* two CLK32 periods */ 4162306a36Sopenharmony_ci #cooling-cells = <2>; 4262306a36Sopenharmony_ci }; 4362306a36Sopenharmony_ci 4462306a36Sopenharmony_ci cpu@1 { 4562306a36Sopenharmony_ci compatible = "arm,cortex-a9"; 4662306a36Sopenharmony_ci reg = <1>; 4762306a36Sopenharmony_ci next-level-cache = <&L2>; 4862306a36Sopenharmony_ci }; 4962306a36Sopenharmony_ci 5062306a36Sopenharmony_ci cpu@2 { 5162306a36Sopenharmony_ci compatible = "arm,cortex-a9"; 5262306a36Sopenharmony_ci reg = <2>; 5362306a36Sopenharmony_ci next-level-cache = <&L2>; 5462306a36Sopenharmony_ci }; 5562306a36Sopenharmony_ci 5662306a36Sopenharmony_ci cpu@3 { 5762306a36Sopenharmony_ci compatible = "arm,cortex-a9"; 5862306a36Sopenharmony_ci reg = <3>; 5962306a36Sopenharmony_ci next-level-cache = <&L2>; 6062306a36Sopenharmony_ci }; 6162306a36Sopenharmony_ci}; 62