162306a36Sopenharmony_ciBinding for the HSDK Generic PLL clock 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciThis binding uses the common clock binding[1]. 462306a36Sopenharmony_ci 562306a36Sopenharmony_ci[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 662306a36Sopenharmony_ci 762306a36Sopenharmony_ciRequired properties: 862306a36Sopenharmony_ci- compatible: should be "snps,hsdk-<name>-pll-clock" 962306a36Sopenharmony_ci "snps,hsdk-core-pll-clock" 1062306a36Sopenharmony_ci "snps,hsdk-gp-pll-clock" 1162306a36Sopenharmony_ci "snps,hsdk-hdmi-pll-clock" 1262306a36Sopenharmony_ci- reg : should contain base register location and length. 1362306a36Sopenharmony_ci- clocks: shall be the input parent clock phandle for the PLL. 1462306a36Sopenharmony_ci- #clock-cells: from common clock binding; Should always be set to 0. 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ciExample: 1762306a36Sopenharmony_ci input_clk: input-clk { 1862306a36Sopenharmony_ci clock-frequency = <33333333>; 1962306a36Sopenharmony_ci compatible = "fixed-clock"; 2062306a36Sopenharmony_ci #clock-cells = <0>; 2162306a36Sopenharmony_ci }; 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci cpu_clk: cpu-clk@0 { 2462306a36Sopenharmony_ci compatible = "snps,hsdk-core-pll-clock"; 2562306a36Sopenharmony_ci reg = <0x00 0x10>; 2662306a36Sopenharmony_ci #clock-cells = <0>; 2762306a36Sopenharmony_ci clocks = <&input_clk>; 2862306a36Sopenharmony_ci }; 29