162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0+ OR MIT) 262306a36Sopenharmony_ci%YAML 1.2 362306a36Sopenharmony_ci--- 462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/clock/rockchip,rk3308-cru.yaml# 562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 662306a36Sopenharmony_ci 762306a36Sopenharmony_cititle: Rockchip RK3308 Clock and Reset Unit (CRU) 862306a36Sopenharmony_ci 962306a36Sopenharmony_cimaintainers: 1062306a36Sopenharmony_ci - Elaine Zhang <zhangqing@rock-chips.com> 1162306a36Sopenharmony_ci - Heiko Stuebner <heiko@sntech.de> 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_cidescription: | 1462306a36Sopenharmony_ci The RK3308 clock controller generates and supplies clocks to various 1562306a36Sopenharmony_ci controllers within the SoC and also implements a reset controller for SoC 1662306a36Sopenharmony_ci peripherals. 1762306a36Sopenharmony_ci Each clock is assigned an identifier and client nodes can use this identifier 1862306a36Sopenharmony_ci to specify the clock which they consume. All available clocks are defined as 1962306a36Sopenharmony_ci preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be 2062306a36Sopenharmony_ci used in device tree sources. Similar macros exist for the reset sources in 2162306a36Sopenharmony_ci these files. 2262306a36Sopenharmony_ci There are several clocks that are generated outside the SoC. It is expected 2362306a36Sopenharmony_ci that they are defined using standard clock bindings with following 2462306a36Sopenharmony_ci clock-output-names: 2562306a36Sopenharmony_ci - "xin24m" - crystal input - required 2662306a36Sopenharmony_ci - "xin32k" - rtc clock - optional 2762306a36Sopenharmony_ci - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", 2862306a36Sopenharmony_ci "mclk_i2s2_8ch_in", "mclk_i2s3_8ch_in", 2962306a36Sopenharmony_ci "mclk_i2s0_2ch_in", "mclk_i2s1_2ch_in" - external I2S or 3062306a36Sopenharmony_ci SPDIF clock - optional 3162306a36Sopenharmony_ci - "mac_clkin" - external MAC clock - optional 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_ciproperties: 3462306a36Sopenharmony_ci compatible: 3562306a36Sopenharmony_ci enum: 3662306a36Sopenharmony_ci - rockchip,rk3308-cru 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_ci reg: 3962306a36Sopenharmony_ci maxItems: 1 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_ci "#clock-cells": 4262306a36Sopenharmony_ci const: 1 4362306a36Sopenharmony_ci 4462306a36Sopenharmony_ci "#reset-cells": 4562306a36Sopenharmony_ci const: 1 4662306a36Sopenharmony_ci 4762306a36Sopenharmony_ci clocks: 4862306a36Sopenharmony_ci maxItems: 1 4962306a36Sopenharmony_ci 5062306a36Sopenharmony_ci clock-names: 5162306a36Sopenharmony_ci const: xin24m 5262306a36Sopenharmony_ci 5362306a36Sopenharmony_ci rockchip,grf: 5462306a36Sopenharmony_ci $ref: /schemas/types.yaml#/definitions/phandle 5562306a36Sopenharmony_ci description: 5662306a36Sopenharmony_ci Phandle to the syscon managing the "general register files" (GRF), 5762306a36Sopenharmony_ci if missing pll rates are not changeable, due to the missing pll 5862306a36Sopenharmony_ci lock status. 5962306a36Sopenharmony_ci 6062306a36Sopenharmony_cirequired: 6162306a36Sopenharmony_ci - compatible 6262306a36Sopenharmony_ci - reg 6362306a36Sopenharmony_ci - "#clock-cells" 6462306a36Sopenharmony_ci - "#reset-cells" 6562306a36Sopenharmony_ci 6662306a36Sopenharmony_ciadditionalProperties: false 6762306a36Sopenharmony_ci 6862306a36Sopenharmony_ciexamples: 6962306a36Sopenharmony_ci - | 7062306a36Sopenharmony_ci cru: clock-controller@ff500000 { 7162306a36Sopenharmony_ci compatible = "rockchip,rk3308-cru"; 7262306a36Sopenharmony_ci reg = <0xff500000 0x1000>; 7362306a36Sopenharmony_ci rockchip,grf = <&grf>; 7462306a36Sopenharmony_ci #clock-cells = <1>; 7562306a36Sopenharmony_ci #reset-cells = <1>; 7662306a36Sopenharmony_ci }; 77