162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 262306a36Sopenharmony_ci%YAML 1.2 362306a36Sopenharmony_ci--- 462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml# 562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 662306a36Sopenharmony_ci 762306a36Sopenharmony_cititle: Microchip PolarFire Clock Control Module 862306a36Sopenharmony_ci 962306a36Sopenharmony_cimaintainers: 1062306a36Sopenharmony_ci - Daire McNamara <daire.mcnamara@microchip.com> 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_cidescription: | 1362306a36Sopenharmony_ci Microchip PolarFire clock control (CLKCFG) is an integrated clock controller, 1462306a36Sopenharmony_ci which gates and enables all peripheral clocks. 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci This device tree binding describes 33 gate clocks. Clocks are referenced by 1762306a36Sopenharmony_ci user nodes by the CLKCFG node phandle and the clock index in the group, from 1862306a36Sopenharmony_ci 0 to 32. 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_ciproperties: 2162306a36Sopenharmony_ci compatible: 2262306a36Sopenharmony_ci const: microchip,mpfs-clkcfg 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ci reg: 2562306a36Sopenharmony_ci items: 2662306a36Sopenharmony_ci - description: | 2762306a36Sopenharmony_ci clock config registers: 2862306a36Sopenharmony_ci These registers contain enable, reset & divider tables for the, cpu, 2962306a36Sopenharmony_ci axi, ahb and rtc/mtimer reference clocks as well as enable and reset 3062306a36Sopenharmony_ci for the peripheral clocks. 3162306a36Sopenharmony_ci - description: | 3262306a36Sopenharmony_ci mss pll dri registers: 3362306a36Sopenharmony_ci Block of registers responsible for dynamic reconfiguration of the mss 3462306a36Sopenharmony_ci pll 3562306a36Sopenharmony_ci 3662306a36Sopenharmony_ci clocks: 3762306a36Sopenharmony_ci maxItems: 1 3862306a36Sopenharmony_ci 3962306a36Sopenharmony_ci '#clock-cells': 4062306a36Sopenharmony_ci const: 1 4162306a36Sopenharmony_ci description: | 4262306a36Sopenharmony_ci The clock consumer should specify the desired clock by having the clock 4362306a36Sopenharmony_ci ID in its "clocks" phandle cell. 4462306a36Sopenharmony_ci See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of 4562306a36Sopenharmony_ci PolarFire clock IDs. 4662306a36Sopenharmony_ci 4762306a36Sopenharmony_ci resets: 4862306a36Sopenharmony_ci maxItems: 1 4962306a36Sopenharmony_ci 5062306a36Sopenharmony_ci '#reset-cells': 5162306a36Sopenharmony_ci description: 5262306a36Sopenharmony_ci The AHB/AXI peripherals on the PolarFire SoC have reset support, so from 5362306a36Sopenharmony_ci CLK_ENVM to CLK_CFM. The reset consumer should specify the desired 5462306a36Sopenharmony_ci peripheral via the clock ID in its "resets" phandle cell. 5562306a36Sopenharmony_ci See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of 5662306a36Sopenharmony_ci PolarFire clock IDs. 5762306a36Sopenharmony_ci const: 1 5862306a36Sopenharmony_ci 5962306a36Sopenharmony_cirequired: 6062306a36Sopenharmony_ci - compatible 6162306a36Sopenharmony_ci - reg 6262306a36Sopenharmony_ci - clocks 6362306a36Sopenharmony_ci - '#clock-cells' 6462306a36Sopenharmony_ci 6562306a36Sopenharmony_ciadditionalProperties: false 6662306a36Sopenharmony_ci 6762306a36Sopenharmony_ciexamples: 6862306a36Sopenharmony_ci # Clock Config node: 6962306a36Sopenharmony_ci - | 7062306a36Sopenharmony_ci #include <dt-bindings/clock/microchip,mpfs-clock.h> 7162306a36Sopenharmony_ci soc { 7262306a36Sopenharmony_ci #address-cells = <2>; 7362306a36Sopenharmony_ci #size-cells = <2>; 7462306a36Sopenharmony_ci clkcfg: clock-controller@20002000 { 7562306a36Sopenharmony_ci compatible = "microchip,mpfs-clkcfg"; 7662306a36Sopenharmony_ci reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; 7762306a36Sopenharmony_ci clocks = <&ref>; 7862306a36Sopenharmony_ci #clock-cells = <1>; 7962306a36Sopenharmony_ci }; 8062306a36Sopenharmony_ci }; 81