162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
262306a36Sopenharmony_ci%YAML 1.2
362306a36Sopenharmony_ci---
462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/clock/mediatek,mt8186-fhctl.yaml#
562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml#
662306a36Sopenharmony_ci
762306a36Sopenharmony_cititle: MediaTek frequency hopping and spread spectrum clocking control
862306a36Sopenharmony_ci
962306a36Sopenharmony_cimaintainers:
1062306a36Sopenharmony_ci  - Edward-JW Yang <edward-jw.yang@mediatek.com>
1162306a36Sopenharmony_ci
1262306a36Sopenharmony_cidescription: |
1362306a36Sopenharmony_ci  Frequency hopping control (FHCTL) is a piece of hardware that control
1462306a36Sopenharmony_ci  some PLLs to adopt "hopping" mechanism to adjust their frequency.
1562306a36Sopenharmony_ci  Spread spectrum clocking (SSC) is another function provided by this hardware.
1662306a36Sopenharmony_ci
1762306a36Sopenharmony_ciproperties:
1862306a36Sopenharmony_ci  compatible:
1962306a36Sopenharmony_ci    enum:
2062306a36Sopenharmony_ci      - mediatek,mt6795-fhctl
2162306a36Sopenharmony_ci      - mediatek,mt8173-fhctl
2262306a36Sopenharmony_ci      - mediatek,mt8186-fhctl
2362306a36Sopenharmony_ci      - mediatek,mt8192-fhctl
2462306a36Sopenharmony_ci      - mediatek,mt8195-fhctl
2562306a36Sopenharmony_ci
2662306a36Sopenharmony_ci  reg:
2762306a36Sopenharmony_ci    maxItems: 1
2862306a36Sopenharmony_ci
2962306a36Sopenharmony_ci  clocks:
3062306a36Sopenharmony_ci    description: Phandles of the PLL with FHCTL hardware capability.
3162306a36Sopenharmony_ci    minItems: 1
3262306a36Sopenharmony_ci    maxItems: 30
3362306a36Sopenharmony_ci
3462306a36Sopenharmony_ci  mediatek,hopping-ssc-percent:
3562306a36Sopenharmony_ci    description: The percentage of spread spectrum clocking for one PLL.
3662306a36Sopenharmony_ci    minItems: 1
3762306a36Sopenharmony_ci    maxItems: 30
3862306a36Sopenharmony_ci    items:
3962306a36Sopenharmony_ci      default: 0
4062306a36Sopenharmony_ci      minimum: 0
4162306a36Sopenharmony_ci      maximum: 8
4262306a36Sopenharmony_ci
4362306a36Sopenharmony_cirequired:
4462306a36Sopenharmony_ci  - compatible
4562306a36Sopenharmony_ci  - reg
4662306a36Sopenharmony_ci  - clocks
4762306a36Sopenharmony_ci
4862306a36Sopenharmony_ciadditionalProperties: false
4962306a36Sopenharmony_ci
5062306a36Sopenharmony_ciexamples:
5162306a36Sopenharmony_ci  - |
5262306a36Sopenharmony_ci    #include <dt-bindings/clock/mt8186-clk.h>
5362306a36Sopenharmony_ci    fhctl: fhctl@1000ce00 {
5462306a36Sopenharmony_ci        compatible = "mediatek,mt8186-fhctl";
5562306a36Sopenharmony_ci        reg = <0x1000ce00 0x200>;
5662306a36Sopenharmony_ci        clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
5762306a36Sopenharmony_ci        mediatek,hopping-ssc-percent = <3>;
5862306a36Sopenharmony_ci    };
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