162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
262306a36Sopenharmony_ci%YAML 1.2
362306a36Sopenharmony_ci---
462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml#
662306a36Sopenharmony_ci
762306a36Sopenharmony_cititle: MT7621 Clock
862306a36Sopenharmony_ci
962306a36Sopenharmony_cimaintainers:
1062306a36Sopenharmony_ci  - Sergio Paracuellos <sergio.paracuellos@gmail.com>
1162306a36Sopenharmony_ci
1262306a36Sopenharmony_cidescription: |
1362306a36Sopenharmony_ci  The MT7621 has a PLL controller from where the cpu clock is provided
1462306a36Sopenharmony_ci  as well as derived clocks for the bus and the peripherals. It also
1562306a36Sopenharmony_ci  can gate SoC device clocks.
1662306a36Sopenharmony_ci
1762306a36Sopenharmony_ci  Each clock is assigned an identifier and client nodes use this identifier
1862306a36Sopenharmony_ci  to specify the clock which they consume.
1962306a36Sopenharmony_ci
2062306a36Sopenharmony_ci  All these identifiers could be found in:
2162306a36Sopenharmony_ci  [1]: <include/dt-bindings/clock/mt7621-clk.h>.
2262306a36Sopenharmony_ci
2362306a36Sopenharmony_ci  The clocks are provided inside a system controller node.
2462306a36Sopenharmony_ci
2562306a36Sopenharmony_ci  This node is also a reset provider for all the peripherals.
2662306a36Sopenharmony_ci
2762306a36Sopenharmony_ci  Reset related bits are defined in:
2862306a36Sopenharmony_ci  [2]: <include/dt-bindings/reset/mt7621-reset.h>.
2962306a36Sopenharmony_ci
3062306a36Sopenharmony_ciproperties:
3162306a36Sopenharmony_ci  compatible:
3262306a36Sopenharmony_ci    items:
3362306a36Sopenharmony_ci      - const: mediatek,mt7621-sysc
3462306a36Sopenharmony_ci      - const: syscon
3562306a36Sopenharmony_ci
3662306a36Sopenharmony_ci  reg:
3762306a36Sopenharmony_ci    maxItems: 1
3862306a36Sopenharmony_ci
3962306a36Sopenharmony_ci  "#clock-cells":
4062306a36Sopenharmony_ci    description:
4162306a36Sopenharmony_ci      The first cell indicates the clock number, see [1] for available
4262306a36Sopenharmony_ci      clocks.
4362306a36Sopenharmony_ci    const: 1
4462306a36Sopenharmony_ci
4562306a36Sopenharmony_ci  "#reset-cells":
4662306a36Sopenharmony_ci    description:
4762306a36Sopenharmony_ci      The first cell indicates the reset bit within the register, see
4862306a36Sopenharmony_ci      [2] for available resets.
4962306a36Sopenharmony_ci    const: 1
5062306a36Sopenharmony_ci
5162306a36Sopenharmony_ci  ralink,memctl:
5262306a36Sopenharmony_ci    $ref: /schemas/types.yaml#/definitions/phandle
5362306a36Sopenharmony_ci    description:
5462306a36Sopenharmony_ci      phandle of syscon used to control memory registers
5562306a36Sopenharmony_ci
5662306a36Sopenharmony_ci  clock-output-names:
5762306a36Sopenharmony_ci    maxItems: 8
5862306a36Sopenharmony_ci
5962306a36Sopenharmony_cirequired:
6062306a36Sopenharmony_ci  - compatible
6162306a36Sopenharmony_ci  - reg
6262306a36Sopenharmony_ci  - '#clock-cells'
6362306a36Sopenharmony_ci  - ralink,memctl
6462306a36Sopenharmony_ci
6562306a36Sopenharmony_ciadditionalProperties: false
6662306a36Sopenharmony_ci
6762306a36Sopenharmony_ciexamples:
6862306a36Sopenharmony_ci  - |
6962306a36Sopenharmony_ci    #include <dt-bindings/clock/mt7621-clk.h>
7062306a36Sopenharmony_ci
7162306a36Sopenharmony_ci    sysc: sysc@0 {
7262306a36Sopenharmony_ci      compatible = "mediatek,mt7621-sysc", "syscon";
7362306a36Sopenharmony_ci      reg = <0x0 0x100>;
7462306a36Sopenharmony_ci      #clock-cells = <1>;
7562306a36Sopenharmony_ci      #reset-cells = <1>;
7662306a36Sopenharmony_ci      ralink,memctl = <&memc>;
7762306a36Sopenharmony_ci      clock-output-names = "xtal", "cpu", "bus",
7862306a36Sopenharmony_ci                           "50m", "125m", "150m",
7962306a36Sopenharmony_ci                           "250m", "270m";
8062306a36Sopenharmony_ci    };
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