162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
262306a36Sopenharmony_ci%YAML 1.2
362306a36Sopenharmony_ci---
462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/clock/mediatek,mt6795-sys-clock.yaml#
562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml#
662306a36Sopenharmony_ci
762306a36Sopenharmony_cititle: MediaTek System Clock Controller for MT6795
862306a36Sopenharmony_ci
962306a36Sopenharmony_cimaintainers:
1062306a36Sopenharmony_ci  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
1162306a36Sopenharmony_ci  - Chun-Jie Chen <chun-jie.chen@mediatek.com>
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_cidescription:
1462306a36Sopenharmony_ci  The Mediatek system clock controller provides various clocks and system
1562306a36Sopenharmony_ci  configuration like reset and bus protection on MT6795.
1662306a36Sopenharmony_ci
1762306a36Sopenharmony_ciproperties:
1862306a36Sopenharmony_ci  compatible:
1962306a36Sopenharmony_ci    items:
2062306a36Sopenharmony_ci      - enum:
2162306a36Sopenharmony_ci          - mediatek,mt6795-apmixedsys
2262306a36Sopenharmony_ci          - mediatek,mt6795-infracfg
2362306a36Sopenharmony_ci          - mediatek,mt6795-pericfg
2462306a36Sopenharmony_ci          - mediatek,mt6795-topckgen
2562306a36Sopenharmony_ci      - const: syscon
2662306a36Sopenharmony_ci
2762306a36Sopenharmony_ci  reg:
2862306a36Sopenharmony_ci    maxItems: 1
2962306a36Sopenharmony_ci
3062306a36Sopenharmony_ci  '#clock-cells':
3162306a36Sopenharmony_ci    const: 1
3262306a36Sopenharmony_ci
3362306a36Sopenharmony_ci  '#reset-cells':
3462306a36Sopenharmony_ci    const: 1
3562306a36Sopenharmony_ci
3662306a36Sopenharmony_cirequired:
3762306a36Sopenharmony_ci  - compatible
3862306a36Sopenharmony_ci  - reg
3962306a36Sopenharmony_ci  - '#clock-cells'
4062306a36Sopenharmony_ci
4162306a36Sopenharmony_ciadditionalProperties: false
4262306a36Sopenharmony_ci
4362306a36Sopenharmony_ciexamples:
4462306a36Sopenharmony_ci  - |
4562306a36Sopenharmony_ci    soc {
4662306a36Sopenharmony_ci        #address-cells = <2>;
4762306a36Sopenharmony_ci        #size-cells = <2>;
4862306a36Sopenharmony_ci
4962306a36Sopenharmony_ci        topckgen: clock-controller@10000000 {
5062306a36Sopenharmony_ci            compatible = "mediatek,mt6795-topckgen", "syscon";
5162306a36Sopenharmony_ci            reg = <0 0x10000000 0 0x1000>;
5262306a36Sopenharmony_ci            #clock-cells = <1>;
5362306a36Sopenharmony_ci        };
5462306a36Sopenharmony_ci    };
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