162306a36Sopenharmony_ciDevicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciThis device exposes 4 clocks in total: 462306a36Sopenharmony_ci 562306a36Sopenharmony_ci- MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz 662306a36Sopenharmony_ci- MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete 762306a36Sopenharmony_ci frequencies 862306a36Sopenharmony_ci- MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ciMAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set 1162306a36Sopenharmony_cirequests. 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ciRequired properties: 1462306a36Sopenharmony_ci- compatible: "maxim,max9485" 1562306a36Sopenharmony_ci- clocks: Input clock, must provide 27.000 MHz 1662306a36Sopenharmony_ci- clock-names: Must be set to "xclk" 1762306a36Sopenharmony_ci- #clock-cells: From common clock binding; shall be set to 1 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ciOptional properties: 2062306a36Sopenharmony_ci- reset-gpios: GPIO descriptor connected to the #RESET input pin 2162306a36Sopenharmony_ci- vdd-supply: A regulator node for Vdd 2262306a36Sopenharmony_ci- clock-output-names: Name of output clocks, as defined in common clock 2362306a36Sopenharmony_ci bindings 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ciIf not explicitly set, the output names are "mclkout", "clkout", "clkout1" 2662306a36Sopenharmony_ciand "clkout2". 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ciClocks are defined as preprocessor macros in the dt-binding header. 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ciExample: 3162306a36Sopenharmony_ci 3262306a36Sopenharmony_ci #include <dt-bindings/clock/maxim,max9485.h> 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ci xo-27mhz: xo-27mhz { 3562306a36Sopenharmony_ci compatible = "fixed-clock"; 3662306a36Sopenharmony_ci #clock-cells = <0>; 3762306a36Sopenharmony_ci clock-frequency = <27000000>; 3862306a36Sopenharmony_ci }; 3962306a36Sopenharmony_ci 4062306a36Sopenharmony_ci &i2c0 { 4162306a36Sopenharmony_ci max9485: audio-clock@63 { 4262306a36Sopenharmony_ci reg = <0x63>; 4362306a36Sopenharmony_ci compatible = "maxim,max9485"; 4462306a36Sopenharmony_ci clock-names = "xclk"; 4562306a36Sopenharmony_ci clocks = <&xo-27mhz>; 4662306a36Sopenharmony_ci reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; 4762306a36Sopenharmony_ci vdd-supply = <&3v3-reg>; 4862306a36Sopenharmony_ci #clock-cells = <1>; 4962306a36Sopenharmony_ci }; 5062306a36Sopenharmony_ci }; 5162306a36Sopenharmony_ci 5262306a36Sopenharmony_ci // Clock consumer node 5362306a36Sopenharmony_ci 5462306a36Sopenharmony_ci foo@0 { 5562306a36Sopenharmony_ci compatible = "bar,foo"; 5662306a36Sopenharmony_ci /* ... */ 5762306a36Sopenharmony_ci clock-names = "foo-input-clk"; 5862306a36Sopenharmony_ci clocks = <&max9485 MAX9485_CLKOUT1>; 5962306a36Sopenharmony_ci }; 60