162306a36Sopenharmony_ciDevice Tree Clock bindings for Marvell Berlin 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciThis binding uses the common clock binding[1]. 462306a36Sopenharmony_ci 562306a36Sopenharmony_ci[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 662306a36Sopenharmony_ci 762306a36Sopenharmony_ciClock related registers are spread among the chip control registers. Berlin 862306a36Sopenharmony_ciclock node should be a sub-node of the chip controller node. Marvell Berlin2 962306a36Sopenharmony_ci(BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some 1062306a36Sopenharmony_ciminor differences in features and register layout. 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ciRequired properties: 1362306a36Sopenharmony_ci- compatible: must be "marvell,berlin2-clk" or "marvell,berlin2q-clk" 1462306a36Sopenharmony_ci- #clock-cells: must be 1 1562306a36Sopenharmony_ci- clocks: must be the input parent clock phandle 1662306a36Sopenharmony_ci- clock-names: name of the input parent clock 1762306a36Sopenharmony_ci Allowed clock-names for the reference clocks are 1862306a36Sopenharmony_ci "refclk" for the SoCs oscillator input on all SoCs, 1962306a36Sopenharmony_ci and SoC-specific input clocks for 2062306a36Sopenharmony_ci BG2/BG2CD: "video_ext0" for the external video clock input 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ciExample: 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_cichip_clk: clock { 2662306a36Sopenharmony_ci compatible = "marvell,berlin2q-clk"; 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ci #clock-cells = <1>; 2962306a36Sopenharmony_ci clocks = <&refclk>; 3062306a36Sopenharmony_ci clock-names = "refclk"; 3162306a36Sopenharmony_ci}; 32