162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 262306a36Sopenharmony_ci# Copyright 2020 thingy.jp. 362306a36Sopenharmony_ci%YAML 1.2 462306a36Sopenharmony_ci--- 562306a36Sopenharmony_ci$id: http://devicetree.org/schemas/arm/mstar/mstar,smpctrl.yaml# 662306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 762306a36Sopenharmony_ci 862306a36Sopenharmony_cititle: MStar/SigmaStar Armv7 SoC SMP control registers 962306a36Sopenharmony_ci 1062306a36Sopenharmony_cimaintainers: 1162306a36Sopenharmony_ci - Daniel Palmer <daniel@thingy.jp> 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_cidescription: | 1462306a36Sopenharmony_ci MStar/SigmaStar's Armv7 SoCs that have more than one processor 1562306a36Sopenharmony_ci have a region of registers that allow setting the boot address 1662306a36Sopenharmony_ci and a magic number that allows secondary processors to leave 1762306a36Sopenharmony_ci the loop they are parked in by the boot ROM. 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ciproperties: 2062306a36Sopenharmony_ci compatible: 2162306a36Sopenharmony_ci items: 2262306a36Sopenharmony_ci - enum: 2362306a36Sopenharmony_ci - sstar,ssd201-smpctrl # SSD201/SSD202D 2462306a36Sopenharmony_ci - const: mstar,smpctrl 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_ci reg: 2762306a36Sopenharmony_ci maxItems: 1 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_cirequired: 3062306a36Sopenharmony_ci - compatible 3162306a36Sopenharmony_ci - reg 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_ciadditionalProperties: false 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ciexamples: 3662306a36Sopenharmony_ci - | 3762306a36Sopenharmony_ci smpctrl@204000 { 3862306a36Sopenharmony_ci compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl"; 3962306a36Sopenharmony_ci reg = <0x204000 0x200>; 4062306a36Sopenharmony_ci }; 41