162306a36Sopenharmony_ciMediatek ethsys controller 262306a36Sopenharmony_ci============================ 362306a36Sopenharmony_ci 462306a36Sopenharmony_ciThe Mediatek ethsys controller provides various clocks to the system. 562306a36Sopenharmony_ci 662306a36Sopenharmony_ciRequired Properties: 762306a36Sopenharmony_ci 862306a36Sopenharmony_ci- compatible: Should be: 962306a36Sopenharmony_ci - "mediatek,mt2701-ethsys", "syscon" 1062306a36Sopenharmony_ci - "mediatek,mt7622-ethsys", "syscon" 1162306a36Sopenharmony_ci - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon" 1262306a36Sopenharmony_ci - "mediatek,mt7629-ethsys", "syscon" 1362306a36Sopenharmony_ci - "mediatek,mt7981-ethsys", "syscon" 1462306a36Sopenharmony_ci - "mediatek,mt7986-ethsys", "syscon" 1562306a36Sopenharmony_ci- #clock-cells: Must be 1 1662306a36Sopenharmony_ci- #reset-cells: Must be 1 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ciThe ethsys controller uses the common clk binding from 1962306a36Sopenharmony_ciDocumentation/devicetree/bindings/clock/clock-bindings.txt 2062306a36Sopenharmony_ciThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_ciExample: 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ciethsys: clock-controller@1b000000 { 2562306a36Sopenharmony_ci compatible = "mediatek,mt2701-ethsys", "syscon"; 2662306a36Sopenharmony_ci reg = <0 0x1b000000 0 0x1000>; 2762306a36Sopenharmony_ci #clock-cells = <1>; 2862306a36Sopenharmony_ci #reset-cells = <1>; 2962306a36Sopenharmony_ci}; 30