162306a36Sopenharmony_ci=========================================================
262306a36Sopenharmony_ciSecondary CPU enable-method "nuvoton,npcm750-smp" binding
362306a36Sopenharmony_ci=========================================================
462306a36Sopenharmony_ci
562306a36Sopenharmony_ciTo apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
662306a36Sopenharmony_cidefined in the "cpus" node.
762306a36Sopenharmony_ci
862306a36Sopenharmony_ciEnable method name:	"nuvoton,npcm750-smp"
962306a36Sopenharmony_ciCompatible machines:	"nuvoton,npcm750"
1062306a36Sopenharmony_ciCompatible CPUs:	"arm,cortex-a9"
1162306a36Sopenharmony_ciRelated properties:	(none)
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_ciNote:
1462306a36Sopenharmony_ciThis enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
1562306a36Sopenharmony_ci"nuvoton,npcm750-gcr".
1662306a36Sopenharmony_ci
1762306a36Sopenharmony_ciExample:
1862306a36Sopenharmony_ci
1962306a36Sopenharmony_ci	cpus {
2062306a36Sopenharmony_ci		#address-cells = <1>;
2162306a36Sopenharmony_ci		#size-cells = <0>;
2262306a36Sopenharmony_ci		enable-method = "nuvoton,npcm750-smp";
2362306a36Sopenharmony_ci
2462306a36Sopenharmony_ci		cpu@0 {
2562306a36Sopenharmony_ci			device_type = "cpu";
2662306a36Sopenharmony_ci			compatible = "arm,cortex-a9";
2762306a36Sopenharmony_ci			clocks = <&clk NPCM7XX_CLK_CPU>;
2862306a36Sopenharmony_ci			clock-names = "clk_cpu";
2962306a36Sopenharmony_ci			reg = <0>;
3062306a36Sopenharmony_ci			next-level-cache = <&L2>;
3162306a36Sopenharmony_ci		};
3262306a36Sopenharmony_ci
3362306a36Sopenharmony_ci		cpu@1 {
3462306a36Sopenharmony_ci			device_type = "cpu";
3562306a36Sopenharmony_ci			compatible = "arm,cortex-a9";
3662306a36Sopenharmony_ci			clocks = <&clk NPCM7XX_CLK_CPU>;
3762306a36Sopenharmony_ci			clock-names = "clk_cpu";
3862306a36Sopenharmony_ci			reg = <1>;
3962306a36Sopenharmony_ci			next-level-cache = <&L2>;
4062306a36Sopenharmony_ci		};
4162306a36Sopenharmony_ci	};
4262306a36Sopenharmony_ci
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