162306a36Sopenharmony_ci========================================================
262306a36Sopenharmony_ciSecondary CPU enable-method "marvell,berlin-smp" binding
362306a36Sopenharmony_ci========================================================
462306a36Sopenharmony_ci
562306a36Sopenharmony_ciThis document describes the "marvell,berlin-smp" method for enabling secondary
662306a36Sopenharmony_ciCPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
762306a36Sopenharmony_cibe defined in the "cpus" node.
862306a36Sopenharmony_ci
962306a36Sopenharmony_ciEnable method name:	"marvell,berlin-smp"
1062306a36Sopenharmony_ciCompatible machines:	"marvell,berlin2" and "marvell,berlin2q"
1162306a36Sopenharmony_ciCompatible CPUs:	"marvell,pj4b" and "arm,cortex-a9"
1262306a36Sopenharmony_ciRelated properties:	(none)
1362306a36Sopenharmony_ci
1462306a36Sopenharmony_ciNote:
1562306a36Sopenharmony_ciThis enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
1662306a36Sopenharmony_ci"marvell,berlin-cpu-ctrl"[1].
1762306a36Sopenharmony_ci
1862306a36Sopenharmony_ciExample:
1962306a36Sopenharmony_ci
2062306a36Sopenharmony_ci	cpus {
2162306a36Sopenharmony_ci		#address-cells = <1>;
2262306a36Sopenharmony_ci		#size-cells = <0>;
2362306a36Sopenharmony_ci		enable-method = "marvell,berlin-smp";
2462306a36Sopenharmony_ci
2562306a36Sopenharmony_ci		cpu@0 {
2662306a36Sopenharmony_ci			compatible = "marvell,pj4b";
2762306a36Sopenharmony_ci			device_type = "cpu";
2862306a36Sopenharmony_ci			next-level-cache = <&l2>;
2962306a36Sopenharmony_ci			reg = <0>;
3062306a36Sopenharmony_ci		};
3162306a36Sopenharmony_ci
3262306a36Sopenharmony_ci		cpu@1 {
3362306a36Sopenharmony_ci			compatible = "marvell,pj4b";
3462306a36Sopenharmony_ci			device_type = "cpu";
3562306a36Sopenharmony_ci			next-level-cache = <&l2>;
3662306a36Sopenharmony_ci			reg = <1>;
3762306a36Sopenharmony_ci		};
3862306a36Sopenharmony_ci	};
3962306a36Sopenharmony_ci
4062306a36Sopenharmony_ci--
4162306a36Sopenharmony_ci[1] arm/marvell,berlin.txt
42