162306a36Sopenharmony_ci=========================================== 262306a36Sopenharmony_ciAtomic Operation Control (ATOMCTL) Register 362306a36Sopenharmony_ci=========================================== 462306a36Sopenharmony_ci 562306a36Sopenharmony_ciWe Have Atomic Operation Control (ATOMCTL) Register. 662306a36Sopenharmony_ciThis register determines the effect of using a S32C1I instruction 762306a36Sopenharmony_ciwith various combinations of: 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci 1. With and without an Coherent Cache Controller which 1062306a36Sopenharmony_ci can do Atomic Transactions to the memory internally. 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci 2. With and without An Intelligent Memory Controller which 1362306a36Sopenharmony_ci can do Atomic Transactions itself. 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ciThe Core comes up with a default value of for the three types of cache ops:: 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ci 0x28: (WB: Internal, WT: Internal, BY:Exception) 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ciOn the FPGA Cards we typically simulate an Intelligent Memory controller 2062306a36Sopenharmony_ciwhich can implement RCW transactions. For FPGA cards with an External 2162306a36Sopenharmony_ciMemory controller we let it to the atomic operations internally while 2262306a36Sopenharmony_cidoing a Cached (WB) transaction and use the Memory RCW for un-cached 2362306a36Sopenharmony_cioperations. 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ciFor systems without an coherent cache controller, non-MX, we always 2662306a36Sopenharmony_ciuse the memory controllers RCW, though non-MX controllers likely 2762306a36Sopenharmony_cisupport the Internal Operation. 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ciCUSTOMER-WARNING: 3062306a36Sopenharmony_ci Virtually all customers buy their memory controllers from vendors that 3162306a36Sopenharmony_ci don't support atomic RCW memory transactions and will likely want to 3262306a36Sopenharmony_ci configure this register to not use RCW. 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ciDevelopers might find using RCW in Bypass mode convenient when testing 3562306a36Sopenharmony_ciwith the cache being bypassed; for example studying cache alias problems. 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ciSee Section 4.3.12.4 of ISA; Bits:: 3862306a36Sopenharmony_ci 3962306a36Sopenharmony_ci WB WT BY 4062306a36Sopenharmony_ci 5 4 | 3 2 | 1 0 4162306a36Sopenharmony_ci 4262306a36Sopenharmony_ci========= ================== ================== =============== 4362306a36Sopenharmony_ci 2 Bit 4462306a36Sopenharmony_ci Field 4562306a36Sopenharmony_ci Values WB - Write Back WT - Write Thru BY - Bypass 4662306a36Sopenharmony_ci========= ================== ================== =============== 4762306a36Sopenharmony_ci 0 Exception Exception Exception 4862306a36Sopenharmony_ci 1 RCW Transaction RCW Transaction RCW Transaction 4962306a36Sopenharmony_ci 2 Internal Operation Internal Operation Reserved 5062306a36Sopenharmony_ci 3 Reserved Reserved Reserved 5162306a36Sopenharmony_ci========= ================== ================== =============== 52