162306a36Sopenharmony_ciWhat:		/sys/devices/platform/<platform>/etr3
262306a36Sopenharmony_ciDate:		Apr 2021
362306a36Sopenharmony_ciKernelVersion:	5.13
462306a36Sopenharmony_ciContact:	"Tomas Winkler" <tomas.winkler@intel.com>
562306a36Sopenharmony_ciDescription:
662306a36Sopenharmony_ci		The file exposes "Extended Test Mode Register 3" global
762306a36Sopenharmony_ci		reset bits. The bits are used during an Intel platform
862306a36Sopenharmony_ci		manufacturing process to indicate that consequent reset
962306a36Sopenharmony_ci		of the platform is a "global reset". This type of reset
1062306a36Sopenharmony_ci		is required in order for manufacturing configurations
1162306a36Sopenharmony_ci		to take effect.
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_ci		Display global reset setting bits for PMC.
1462306a36Sopenharmony_ci
1562306a36Sopenharmony_ci			* bit 31 - global reset is locked
1662306a36Sopenharmony_ci			* bit 20 - global reset is set
1762306a36Sopenharmony_ci
1862306a36Sopenharmony_ci		Writing bit 20 value to the etr3 will induce
1962306a36Sopenharmony_ci		a platform "global reset" upon consequent platform reset,
2062306a36Sopenharmony_ci		in case the register is not locked.
2162306a36Sopenharmony_ci		The "global reset bit" should be locked on a production
2262306a36Sopenharmony_ci		system and the file is in read-only mode.
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