162306a36Sopenharmony_ciWhat:		/sys/devices/system/machinecheck/machinecheckX/
262306a36Sopenharmony_ciContact:	Andi Kleen <ak@linux.intel.com>
362306a36Sopenharmony_ciDate:		Feb, 2007
462306a36Sopenharmony_ciDescription:
562306a36Sopenharmony_ci		(X = CPU number)
662306a36Sopenharmony_ci
762306a36Sopenharmony_ci		Machine checks report internal hardware error conditions
862306a36Sopenharmony_ci		detected by the CPU. Uncorrected errors typically cause a
962306a36Sopenharmony_ci		machine check (often with panic), corrected ones cause a
1062306a36Sopenharmony_ci		machine check log entry.
1162306a36Sopenharmony_ci
1262306a36Sopenharmony_ci		For more details about the x86 machine check architecture
1362306a36Sopenharmony_ci		see the Intel and AMD architecture manuals from their
1462306a36Sopenharmony_ci		developer websites.
1562306a36Sopenharmony_ci
1662306a36Sopenharmony_ci		For more details about the architecture
1762306a36Sopenharmony_ci		see http://one.firstfloor.org/~andi/mce.pdf
1862306a36Sopenharmony_ci
1962306a36Sopenharmony_ci		Each CPU has its own directory.
2062306a36Sopenharmony_ci
2162306a36Sopenharmony_ciWhat:		/sys/devices/system/machinecheck/machinecheckX/bank<Y>
2262306a36Sopenharmony_ciContact:	Andi Kleen <ak@linux.intel.com>
2362306a36Sopenharmony_ciDate:		Feb, 2007
2462306a36Sopenharmony_ciDescription:
2562306a36Sopenharmony_ci		(Y bank number)
2662306a36Sopenharmony_ci
2762306a36Sopenharmony_ci		64bit Hex bitmask enabling/disabling specific subevents for
2862306a36Sopenharmony_ci		bank Y.
2962306a36Sopenharmony_ci
3062306a36Sopenharmony_ci		When a bit in the bitmask is zero then the respective
3162306a36Sopenharmony_ci		subevent will not be reported.
3262306a36Sopenharmony_ci
3362306a36Sopenharmony_ci		By default all events are enabled.
3462306a36Sopenharmony_ci
3562306a36Sopenharmony_ci		Note that BIOS maintain another mask to disable specific events
3662306a36Sopenharmony_ci		per bank.  This is not visible here
3762306a36Sopenharmony_ci
3862306a36Sopenharmony_ciWhat:		/sys/devices/system/machinecheck/machinecheckX/check_interval
3962306a36Sopenharmony_ciContact:	Andi Kleen <ak@linux.intel.com>
4062306a36Sopenharmony_ciDate:		Feb, 2007
4162306a36Sopenharmony_ciDescription:
4262306a36Sopenharmony_ci		The entries appear for each CPU, but they are truly shared
4362306a36Sopenharmony_ci		between all CPUs.
4462306a36Sopenharmony_ci
4562306a36Sopenharmony_ci		How often to poll for corrected machine check errors, in
4662306a36Sopenharmony_ci		seconds (Note output is hexadecimal). Default 5 minutes.
4762306a36Sopenharmony_ci		When the poller finds MCEs it triggers an exponential speedup
4862306a36Sopenharmony_ci		(poll more often) on the polling interval.  When the poller
4962306a36Sopenharmony_ci		stops finding MCEs, it triggers an exponential backoff
5062306a36Sopenharmony_ci		(poll less often) on the polling interval. The check_interval
5162306a36Sopenharmony_ci		variable is both the initial and maximum polling interval.
5262306a36Sopenharmony_ci		0 means no polling for corrected machine check errors
5362306a36Sopenharmony_ci		(but some corrected errors might be still reported
5462306a36Sopenharmony_ci		in other ways)
5562306a36Sopenharmony_ci
5662306a36Sopenharmony_ciWhat:		/sys/devices/system/machinecheck/machinecheckX/trigger
5762306a36Sopenharmony_ciContact:	Andi Kleen <ak@linux.intel.com>
5862306a36Sopenharmony_ciDate:		Feb, 2007
5962306a36Sopenharmony_ciDescription:
6062306a36Sopenharmony_ci		The entries appear for each CPU, but they are truly shared
6162306a36Sopenharmony_ci		between all CPUs.
6262306a36Sopenharmony_ci
6362306a36Sopenharmony_ci		Program to run when a machine check event is detected.
6462306a36Sopenharmony_ci		This is an alternative to running mcelog regularly from cron
6562306a36Sopenharmony_ci		and allows to detect events faster.
6662306a36Sopenharmony_ci
6762306a36Sopenharmony_ciWhat:		/sys/devices/system/machinecheck/machinecheckX/monarch_timeout
6862306a36Sopenharmony_ciContact:	Andi Kleen <ak@linux.intel.com>
6962306a36Sopenharmony_ciDate:		Feb, 2007
7062306a36Sopenharmony_ciDescription:
7162306a36Sopenharmony_ci		How long to wait for the other CPUs to machine check too on a
7262306a36Sopenharmony_ci		exception. 0 to disable waiting for other CPUs.
7362306a36Sopenharmony_ci
7462306a36Sopenharmony_ci		Unit: us
7562306a36Sopenharmony_ci
7662306a36Sopenharmony_ciWhat:		/sys/devices/system/machinecheck/machinecheckX/ignore_ce
7762306a36Sopenharmony_ciContact:	Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
7862306a36Sopenharmony_ciDate:		Jun 2009
7962306a36Sopenharmony_ciDescription:
8062306a36Sopenharmony_ci		Disables polling and CMCI for corrected errors.
8162306a36Sopenharmony_ci		All corrected events are not cleared and kept in bank MSRs.
8262306a36Sopenharmony_ci
8362306a36Sopenharmony_ciWhat:		/sys/devices/system/machinecheck/machinecheckX/dont_log_ce
8462306a36Sopenharmony_ciContact:	Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
8562306a36Sopenharmony_ciDate:		Jun 2009
8662306a36Sopenharmony_ciDescription:
8762306a36Sopenharmony_ci		Disables logging for corrected errors.
8862306a36Sopenharmony_ci		All reported corrected errors will be cleared silently.
8962306a36Sopenharmony_ci
9062306a36Sopenharmony_ci		This option will be useful if you never care about corrected
9162306a36Sopenharmony_ci		errors.
9262306a36Sopenharmony_ci
9362306a36Sopenharmony_ciWhat:		/sys/devices/system/machinecheck/machinecheckX/cmci_disabled
9462306a36Sopenharmony_ciContact:	Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
9562306a36Sopenharmony_ciDate:		Jun 2009
9662306a36Sopenharmony_ciDescription:
9762306a36Sopenharmony_ci		Disables the CMCI feature.
98