162306a36Sopenharmony_ciWhat:		/sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status
262306a36Sopenharmony_ciDate:		February 2023
362306a36Sopenharmony_ciKernelVersion:	6.4
462306a36Sopenharmony_ciContact:	Nava kishore Manne <nava.kishore.manne@amd.com>
562306a36Sopenharmony_ciDescription:	(RO) Read fpga status.
662306a36Sopenharmony_ci		Read returns a hexadecimal value that tells the current status
762306a36Sopenharmony_ci		of the FPGA device. Each bit position in the status value is
862306a36Sopenharmony_ci		described Below(see ug570 chapter 9).
962306a36Sopenharmony_ci		https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
1062306a36Sopenharmony_ci
1162306a36Sopenharmony_ci		======================  ==============================================
1262306a36Sopenharmony_ci		BIT(0)			0: No CRC error
1362306a36Sopenharmony_ci					1: CRC error
1462306a36Sopenharmony_ci
1562306a36Sopenharmony_ci		BIT(1)			0: Decryptor security not set
1662306a36Sopenharmony_ci					1: Decryptor security set
1762306a36Sopenharmony_ci
1862306a36Sopenharmony_ci		BIT(2)			0: MMCMs/PLLs are not locked
1962306a36Sopenharmony_ci					1: MMCMs/PLLs are locked
2062306a36Sopenharmony_ci
2162306a36Sopenharmony_ci		BIT(3)			0: DCI not matched
2262306a36Sopenharmony_ci					1: DCI matched
2362306a36Sopenharmony_ci
2462306a36Sopenharmony_ci		BIT(4)			0: Start-up sequence has not finished
2562306a36Sopenharmony_ci					1: Start-up sequence has finished
2662306a36Sopenharmony_ci
2762306a36Sopenharmony_ci		BIT(5)			0: All I/Os are placed in High-Z state
2862306a36Sopenharmony_ci					1: All I/Os behave as configured
2962306a36Sopenharmony_ci
3062306a36Sopenharmony_ci		BIT(6)			0: Flip-flops and block RAM are write disabled
3162306a36Sopenharmony_ci					1: Flip-flops and block RAM are write enabled
3262306a36Sopenharmony_ci
3362306a36Sopenharmony_ci		BIT(7)			0: GHIGH_B_STATUS asserted
3462306a36Sopenharmony_ci					1: GHIGH_B_STATUS deasserted
3562306a36Sopenharmony_ci
3662306a36Sopenharmony_ci		BIT(8) to BIT(10)	Status of the mode pins
3762306a36Sopenharmony_ci
3862306a36Sopenharmony_ci		BIT(11)			0: Initialization has not finished
3962306a36Sopenharmony_ci					1: Initialization finished
4062306a36Sopenharmony_ci
4162306a36Sopenharmony_ci		BIT(12)			Value on INIT_B_PIN pin
4262306a36Sopenharmony_ci
4362306a36Sopenharmony_ci		BIT(13)			0: Signal not released
4462306a36Sopenharmony_ci					1: Signal released
4562306a36Sopenharmony_ci
4662306a36Sopenharmony_ci		BIT(14)			Value on DONE_PIN pin.
4762306a36Sopenharmony_ci
4862306a36Sopenharmony_ci		BIT(15)			0: No IDCODE_ERROR
4962306a36Sopenharmony_ci					1: IDCODE_ERROR
5062306a36Sopenharmony_ci
5162306a36Sopenharmony_ci		BIT(16)			0: No SECURITY_ERROR
5262306a36Sopenharmony_ci					1: SECURITY_ERROR
5362306a36Sopenharmony_ci
5462306a36Sopenharmony_ci		BIT(17)			System Monitor over-temperature if set
5562306a36Sopenharmony_ci
5662306a36Sopenharmony_ci		BIT(18) to BIT(20)	Start-up state machine (0 to 7)
5762306a36Sopenharmony_ci					Phase 0 = 000
5862306a36Sopenharmony_ci					Phase 1 = 001
5962306a36Sopenharmony_ci					Phase 2 = 011
6062306a36Sopenharmony_ci					Phase 3 = 010
6162306a36Sopenharmony_ci					Phase 4 = 110
6262306a36Sopenharmony_ci					Phase 5 = 111
6362306a36Sopenharmony_ci					Phase 6 = 101
6462306a36Sopenharmony_ci					Phase 7 = 100
6562306a36Sopenharmony_ci
6662306a36Sopenharmony_ci		BIT(25) to BIT(26)	Indicates the detected bus width
6762306a36Sopenharmony_ci					00 = x1
6862306a36Sopenharmony_ci					01 = x8
6962306a36Sopenharmony_ci					10 = x16
7062306a36Sopenharmony_ci					11 = x32
7162306a36Sopenharmony_ci		======================  ==============================================
7262306a36Sopenharmony_ci
7362306a36Sopenharmony_ci		The other bits are reserved.
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