162306a36Sopenharmony_ciWhat:		/sys/devices/platform/HISI04Bx:00/chipX/all_linked
262306a36Sopenharmony_ciWhat:		/sys/devices/platform/HISI04Bx:00/chipX/linked_full_lane
362306a36Sopenharmony_ciWhat:		/sys/devices/platform/HISI04Bx:00/chipX/crc_err_cnt
462306a36Sopenharmony_ciDate:		November 2023
562306a36Sopenharmony_ciKernelVersion:	6.6
662306a36Sopenharmony_ciContact:	Huisong Li <lihuisong@huawei.org>
762306a36Sopenharmony_ciDescription:
862306a36Sopenharmony_ci		The /sys/devices/platform/HISI04Bx:00/chipX/ directory
962306a36Sopenharmony_ci		contains read-only attributes exposing some summarization
1062306a36Sopenharmony_ci		information of all HCCS ports under a specified chip.
1162306a36Sopenharmony_ci		The X in 'chipX' indicates the Xth chip on platform.
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_ci		There are following attributes in this directory:
1462306a36Sopenharmony_ci
1562306a36Sopenharmony_ci		================= ==== =========================================
1662306a36Sopenharmony_ci		all_linked:       (RO) if all enabled ports on this chip are
1762306a36Sopenharmony_ci				       linked (bool).
1862306a36Sopenharmony_ci		linked_full_lane: (RO) if all linked ports on this chip are full
1962306a36Sopenharmony_ci				       lane (bool).
2062306a36Sopenharmony_ci		crc_err_cnt:      (RO) total CRC err count for all ports on this
2162306a36Sopenharmony_ci				       chip.
2262306a36Sopenharmony_ci		================= ==== =========================================
2362306a36Sopenharmony_ci
2462306a36Sopenharmony_ciWhat:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/all_linked
2562306a36Sopenharmony_ciWhat:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/linked_full_lane
2662306a36Sopenharmony_ciWhat:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/crc_err_cnt
2762306a36Sopenharmony_ciDate:		November 2023
2862306a36Sopenharmony_ciKernelVersion:	6.6
2962306a36Sopenharmony_ciContact:	Huisong Li <lihuisong@huawei.org>
3062306a36Sopenharmony_ciDescription:
3162306a36Sopenharmony_ci		The /sys/devices/platform/HISI04Bx:00/chipX/dieY/ directory
3262306a36Sopenharmony_ci		contains read-only attributes exposing some summarization
3362306a36Sopenharmony_ci		information of all HCCS ports under a specified die.
3462306a36Sopenharmony_ci		The Y in 'dieY' indicates the hardware id of the die on chip who
3562306a36Sopenharmony_ci		has chip id X.
3662306a36Sopenharmony_ci
3762306a36Sopenharmony_ci		There are following attributes in this directory:
3862306a36Sopenharmony_ci
3962306a36Sopenharmony_ci		================= ==== =========================================
4062306a36Sopenharmony_ci		all_linked:       (RO) if all enabled ports on this die are
4162306a36Sopenharmony_ci				       linked (bool).
4262306a36Sopenharmony_ci		linked_full_lane: (RO) if all linked ports on this die are full
4362306a36Sopenharmony_ci				       lane (bool).
4462306a36Sopenharmony_ci		crc_err_cnt:      (RO) total CRC err count for all ports on this
4562306a36Sopenharmony_ci				       die.
4662306a36Sopenharmony_ci		================= ==== =========================================
4762306a36Sopenharmony_ci
4862306a36Sopenharmony_ciWhat:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/type
4962306a36Sopenharmony_ciWhat:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/lane_mode
5062306a36Sopenharmony_ciWhat:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/enable
5162306a36Sopenharmony_ciWhat:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/cur_lane_num
5262306a36Sopenharmony_ciWhat:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/link_fsm
5362306a36Sopenharmony_ciWhat:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/lane_mask
5462306a36Sopenharmony_ciWhat:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/crc_err_cnt
5562306a36Sopenharmony_ciDate:		November 2023
5662306a36Sopenharmony_ciKernelVersion:	6.6
5762306a36Sopenharmony_ciContact:	Huisong Li <lihuisong@huawei.org>
5862306a36Sopenharmony_ciDescription:
5962306a36Sopenharmony_ci		The /sys/devices/platform/HISI04Bx/chipX/dieX/hccsN/ directory
6062306a36Sopenharmony_ci		contains read-only attributes exposing information about
6162306a36Sopenharmony_ci		a HCCS port. The N value in 'hccsN' indicates this port id.
6262306a36Sopenharmony_ci		The X in 'chipX' indicates the ID of the chip to which the
6362306a36Sopenharmony_ci		HCCS port belongs. For example, X ranges from to 'n - 1' if the
6462306a36Sopenharmony_ci		chip number on platform is n.
6562306a36Sopenharmony_ci		The Y in 'dieY' indicates the hardware id of the die to which
6662306a36Sopenharmony_ci		the hccs port belongs.
6762306a36Sopenharmony_ci		Note: type, lane_mode and enable are fixed attributes on running
6862306a36Sopenharmony_ci		platform.
6962306a36Sopenharmony_ci
7062306a36Sopenharmony_ci		The HCCS port have the following attributes:
7162306a36Sopenharmony_ci
7262306a36Sopenharmony_ci		============= ==== =============================================
7362306a36Sopenharmony_ci		type:         (RO) port type (string), e.g. HCCS-v1 -> H32
7462306a36Sopenharmony_ci		lane_mode:    (RO) the lane mode of this port (string), e.g. x8
7562306a36Sopenharmony_ci		enable:       (RO) indicate if this port is enabled (bool).
7662306a36Sopenharmony_ci		cur_lane_num: (RO) current lane number of this port.
7762306a36Sopenharmony_ci		link_fsm:     (RO) link finite state machine of this port.
7862306a36Sopenharmony_ci		lane_mask:    (RO) current lane mask of this port, every bit
7962306a36Sopenharmony_ci			           indicates a lane.
8062306a36Sopenharmony_ci		crc_err_cnt:  (RO) CRC err count on this port.
8162306a36Sopenharmony_ci		============= ==== =============================================
82