162306a36Sopenharmony_ciWhat: /sys/bus/coresight/devices/<memory_map>.stm/enable_source 262306a36Sopenharmony_ciDate: April 2016 362306a36Sopenharmony_ciKernelVersion: 4.7 462306a36Sopenharmony_ciContact: Mathieu Poirier <mathieu.poirier@linaro.org> 562306a36Sopenharmony_ciDescription: (RW) Enable/disable tracing on this specific trace macrocell. 662306a36Sopenharmony_ci Enabling the trace macrocell implies it has been configured 762306a36Sopenharmony_ci properly and a sink has been identified for it. The path 862306a36Sopenharmony_ci of coresight components linking the source to the sink is 962306a36Sopenharmony_ci configured and managed automatically by the coresight framework. 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ciWhat: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_enable 1262306a36Sopenharmony_ciDate: April 2016 1362306a36Sopenharmony_ciKernelVersion: 4.7 1462306a36Sopenharmony_ciContact: Mathieu Poirier <mathieu.poirier@linaro.org> 1562306a36Sopenharmony_ciDescription: (RW) Provides access to the HW event enable register, used in 1662306a36Sopenharmony_ci conjunction with HW event bank select register. 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ciWhat: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_select 1962306a36Sopenharmony_ciDate: April 2016 2062306a36Sopenharmony_ciKernelVersion: 4.7 2162306a36Sopenharmony_ciContact: Mathieu Poirier <mathieu.poirier@linaro.org> 2262306a36Sopenharmony_ciDescription: (RW) Gives access to the HW event block select register 2362306a36Sopenharmony_ci (STMHEBSR) in order to configure up to 256 channels. Used in 2462306a36Sopenharmony_ci conjunction with "hwevent_enable" register as described above. 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_ciWhat: /sys/bus/coresight/devices/<memory_map>.stm/port_enable 2762306a36Sopenharmony_ciDate: April 2016 2862306a36Sopenharmony_ciKernelVersion: 4.7 2962306a36Sopenharmony_ciContact: Mathieu Poirier <mathieu.poirier@linaro.org> 3062306a36Sopenharmony_ciDescription: (RW) Provides access to the stimulus port enable register 3162306a36Sopenharmony_ci (STMSPER). Used in conjunction with "port_select" described 3262306a36Sopenharmony_ci below. 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ciWhat: /sys/bus/coresight/devices/<memory_map>.stm/port_select 3562306a36Sopenharmony_ciDate: April 2016 3662306a36Sopenharmony_ciKernelVersion: 4.7 3762306a36Sopenharmony_ciContact: Mathieu Poirier <mathieu.poirier@linaro.org> 3862306a36Sopenharmony_ciDescription: (RW) Used to determine which bank of stimulus port bit in 3962306a36Sopenharmony_ci register STMSPER (see above) apply to. 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_ciWhat: /sys/bus/coresight/devices/<memory_map>.stm/status 4262306a36Sopenharmony_ciDate: April 2016 4362306a36Sopenharmony_ciKernelVersion: 4.7 4462306a36Sopenharmony_ciContact: Mathieu Poirier <mathieu.poirier@linaro.org> 4562306a36Sopenharmony_ciDescription: (Read) List various control and status registers. The specific 4662306a36Sopenharmony_ci layout and content is driver specific. 4762306a36Sopenharmony_ci 4862306a36Sopenharmony_ciWhat: /sys/bus/coresight/devices/<memory_map>.stm/traceid 4962306a36Sopenharmony_ciDate: April 2016 5062306a36Sopenharmony_ciKernelVersion: 4.7 5162306a36Sopenharmony_ciContact: Mathieu Poirier <mathieu.poirier@linaro.org> 5262306a36Sopenharmony_ciDescription: (RW) Holds the trace ID that will appear in the trace stream 5362306a36Sopenharmony_ci coming from this trace entity. 54