1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright 2014, Michael Ellerman, IBM Corp. 4 */ 5 6#ifndef _SELFTESTS_POWERPC_REG_H 7#define _SELFTESTS_POWERPC_REG_H 8 9#define __stringify_1(x) #x 10#define __stringify(x) __stringify_1(x) 11 12#define mfspr(rn) ({unsigned long rval; \ 13 asm volatile("mfspr %0," _str(rn) \ 14 : "=r" (rval)); rval; }) 15#define mtspr(rn, v) asm volatile("mtspr " _str(rn) ",%0" : \ 16 : "r" ((unsigned long)(v)) \ 17 : "memory") 18 19#define mb() asm volatile("sync" : : : "memory"); 20#define barrier() asm volatile("" : : : "memory"); 21 22#define SPRN_MMCR2 769 23#define SPRN_MMCRA 770 24#define SPRN_MMCR0 779 25#define MMCR0_PMAO 0x00000080 26#define MMCR0_PMAE 0x04000000 27#define MMCR0_FC 0x80000000 28#define SPRN_EBBHR 804 29#define SPRN_EBBRR 805 30#define SPRN_BESCR 806 /* Branch event status & control register */ 31#define SPRN_BESCRS 800 /* Branch event status & control set (1 bits set to 1) */ 32#define SPRN_BESCRSU 801 /* Branch event status & control set upper */ 33#define SPRN_BESCRR 802 /* Branch event status & control REset (1 bits set to 0) */ 34#define SPRN_BESCRRU 803 /* Branch event status & control REset upper */ 35 36#define BESCR_PMEO 0x1 /* PMU Event-based exception Occurred */ 37#define BESCR_PME (0x1ul << 32) /* PMU Event-based exception Enable */ 38 39#define SPRN_PMC1 771 40#define SPRN_PMC2 772 41#define SPRN_PMC3 773 42#define SPRN_PMC4 774 43#define SPRN_PMC5 775 44#define SPRN_PMC6 776 45 46#define SPRN_SIAR 780 47#define SPRN_SDAR 781 48#define SPRN_SIER 768 49 50#define SPRN_TEXASR 0x82 /* Transaction Exception and Status Register */ 51#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */ 52#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */ 53#define SPRN_TAR 0x32f /* Target Address Register */ 54 55#define SPRN_DSCR_PRIV 0x11 /* Privilege State DSCR */ 56#define SPRN_DSCR 0x03 /* Data Stream Control Register */ 57#define SPRN_PPR 896 /* Program Priority Register */ 58#define SPRN_AMR 13 /* Authority Mask Register - problem state */ 59 60#define set_amr(v) asm volatile("isync;" \ 61 "mtspr " __stringify(SPRN_AMR) ",%0;" \ 62 "isync" : \ 63 : "r" ((unsigned long)(v)) \ 64 : "memory") 65 66/* TEXASR register bits */ 67#define TEXASR_FC 0xFE00000000000000 68#define TEXASR_FP 0x0100000000000000 69#define TEXASR_DA 0x0080000000000000 70#define TEXASR_NO 0x0040000000000000 71#define TEXASR_FO 0x0020000000000000 72#define TEXASR_SIC 0x0010000000000000 73#define TEXASR_NTC 0x0008000000000000 74#define TEXASR_TC 0x0004000000000000 75#define TEXASR_TIC 0x0002000000000000 76#define TEXASR_IC 0x0001000000000000 77#define TEXASR_IFC 0x0000800000000000 78#define TEXASR_ABT 0x0000000100000000 79#define TEXASR_SPD 0x0000000080000000 80#define TEXASR_HV 0x0000000020000000 81#define TEXASR_PR 0x0000000010000000 82#define TEXASR_FS 0x0000000008000000 83#define TEXASR_TE 0x0000000004000000 84#define TEXASR_ROT 0x0000000002000000 85 86/* MSR register bits */ 87#define MSR_TS_S_LG 33 /* Trans Mem state: Suspended */ 88#define MSR_TS_T_LG 34 /* Trans Mem state: Active */ 89 90#define __MASK(X) (1UL<<(X)) 91 92/* macro to check TM MSR bits */ 93#define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */ 94#define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */ 95 96/* Vector Instructions */ 97#define VSX_XX1(xs, ra, rb) (((xs) & 0x1f) << 21 | ((ra) << 16) | \ 98 ((rb) << 11) | (((xs) >> 5))) 99#define STXVD2X(xs, ra, rb) .long (0x7c000798 | VSX_XX1((xs), (ra), (rb))) 100#define LXVD2X(xs, ra, rb) .long (0x7c000698 | VSX_XX1((xs), (ra), (rb))) 101 102#define ASM_LOAD_GPR_IMMED(_asm_symbol_name_immed) \ 103 "li 14, %[" #_asm_symbol_name_immed "];" \ 104 "li 15, %[" #_asm_symbol_name_immed "];" \ 105 "li 16, %[" #_asm_symbol_name_immed "];" \ 106 "li 17, %[" #_asm_symbol_name_immed "];" \ 107 "li 18, %[" #_asm_symbol_name_immed "];" \ 108 "li 19, %[" #_asm_symbol_name_immed "];" \ 109 "li 20, %[" #_asm_symbol_name_immed "];" \ 110 "li 21, %[" #_asm_symbol_name_immed "];" \ 111 "li 22, %[" #_asm_symbol_name_immed "];" \ 112 "li 23, %[" #_asm_symbol_name_immed "];" \ 113 "li 24, %[" #_asm_symbol_name_immed "];" \ 114 "li 25, %[" #_asm_symbol_name_immed "];" \ 115 "li 26, %[" #_asm_symbol_name_immed "];" \ 116 "li 27, %[" #_asm_symbol_name_immed "];" \ 117 "li 28, %[" #_asm_symbol_name_immed "];" \ 118 "li 29, %[" #_asm_symbol_name_immed "];" \ 119 "li 30, %[" #_asm_symbol_name_immed "];" \ 120 "li 31, %[" #_asm_symbol_name_immed "];" 121 122#define ASM_LOAD_FPR_SINGLE_PRECISION(_asm_symbol_name_addr) \ 123 "lfs 0, 0(%[" #_asm_symbol_name_addr "]);" \ 124 "lfs 1, 0(%[" #_asm_symbol_name_addr "]);" \ 125 "lfs 2, 0(%[" #_asm_symbol_name_addr "]);" \ 126 "lfs 3, 0(%[" #_asm_symbol_name_addr "]);" \ 127 "lfs 4, 0(%[" #_asm_symbol_name_addr "]);" \ 128 "lfs 5, 0(%[" #_asm_symbol_name_addr "]);" \ 129 "lfs 6, 0(%[" #_asm_symbol_name_addr "]);" \ 130 "lfs 7, 0(%[" #_asm_symbol_name_addr "]);" \ 131 "lfs 8, 0(%[" #_asm_symbol_name_addr "]);" \ 132 "lfs 9, 0(%[" #_asm_symbol_name_addr "]);" \ 133 "lfs 10, 0(%[" #_asm_symbol_name_addr "]);" \ 134 "lfs 11, 0(%[" #_asm_symbol_name_addr "]);" \ 135 "lfs 12, 0(%[" #_asm_symbol_name_addr "]);" \ 136 "lfs 13, 0(%[" #_asm_symbol_name_addr "]);" \ 137 "lfs 14, 0(%[" #_asm_symbol_name_addr "]);" \ 138 "lfs 15, 0(%[" #_asm_symbol_name_addr "]);" \ 139 "lfs 16, 0(%[" #_asm_symbol_name_addr "]);" \ 140 "lfs 17, 0(%[" #_asm_symbol_name_addr "]);" \ 141 "lfs 18, 0(%[" #_asm_symbol_name_addr "]);" \ 142 "lfs 19, 0(%[" #_asm_symbol_name_addr "]);" \ 143 "lfs 20, 0(%[" #_asm_symbol_name_addr "]);" \ 144 "lfs 21, 0(%[" #_asm_symbol_name_addr "]);" \ 145 "lfs 22, 0(%[" #_asm_symbol_name_addr "]);" \ 146 "lfs 23, 0(%[" #_asm_symbol_name_addr "]);" \ 147 "lfs 24, 0(%[" #_asm_symbol_name_addr "]);" \ 148 "lfs 25, 0(%[" #_asm_symbol_name_addr "]);" \ 149 "lfs 26, 0(%[" #_asm_symbol_name_addr "]);" \ 150 "lfs 27, 0(%[" #_asm_symbol_name_addr "]);" \ 151 "lfs 28, 0(%[" #_asm_symbol_name_addr "]);" \ 152 "lfs 29, 0(%[" #_asm_symbol_name_addr "]);" \ 153 "lfs 30, 0(%[" #_asm_symbol_name_addr "]);" \ 154 "lfs 31, 0(%[" #_asm_symbol_name_addr "]);" 155 156#ifndef __ASSEMBLER__ 157void store_gpr(unsigned long *addr); 158void load_gpr(unsigned long *addr); 159void load_fpr_single_precision(float *addr); 160void store_fpr_single_precision(float *addr); 161#endif /* end of __ASSEMBLER__ */ 162 163#endif /* _SELFTESTS_POWERPC_REG_H */ 164