1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright(C) 2015 Linaro Limited. All rights reserved. 4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org> 5 */ 6 7#ifndef INCLUDE__UTIL_PERF_CS_ETM_H__ 8#define INCLUDE__UTIL_PERF_CS_ETM_H__ 9 10#include "util/event.h" 11#include <linux/bits.h> 12 13struct perf_session; 14 15/* Versionning header in case things need tro change in the future. That way 16 * decoding of old snapshot is still possible. 17 */ 18enum { 19 /* Starting with 0x0 */ 20 CS_HEADER_VERSION_0, 21 /* PMU->type (32 bit), total # of CPUs (32 bit) */ 22 CS_PMU_TYPE_CPUS, 23 CS_ETM_SNAPSHOT, 24 CS_HEADER_VERSION_0_MAX, 25}; 26 27/* Beginning of header common to both ETMv3 and V4 */ 28enum { 29 CS_ETM_MAGIC, 30 CS_ETM_CPU, 31}; 32 33/* ETMv3/PTM metadata */ 34enum { 35 /* Dynamic, configurable parameters */ 36 CS_ETM_ETMCR = CS_ETM_CPU + 1, 37 CS_ETM_ETMTRACEIDR, 38 /* RO, taken from sysFS */ 39 CS_ETM_ETMCCER, 40 CS_ETM_ETMIDR, 41 CS_ETM_PRIV_MAX, 42}; 43 44/* ETMv4 metadata */ 45enum { 46 /* Dynamic, configurable parameters */ 47 CS_ETMV4_TRCCONFIGR = CS_ETM_CPU + 1, 48 CS_ETMV4_TRCTRACEIDR, 49 /* RO, taken from sysFS */ 50 CS_ETMV4_TRCIDR0, 51 CS_ETMV4_TRCIDR1, 52 CS_ETMV4_TRCIDR2, 53 CS_ETMV4_TRCIDR8, 54 CS_ETMV4_TRCAUTHSTATUS, 55 CS_ETMV4_PRIV_MAX, 56}; 57 58/* 59 * ETMv3 exception encoding number: 60 * See Embedded Trace Macrocell spcification (ARM IHI 0014Q) 61 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors. 62 */ 63enum { 64 CS_ETMV3_EXC_NONE = 0, 65 CS_ETMV3_EXC_DEBUG_HALT = 1, 66 CS_ETMV3_EXC_SMC = 2, 67 CS_ETMV3_EXC_HYP = 3, 68 CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4, 69 CS_ETMV3_EXC_JAZELLE_THUMBEE = 5, 70 CS_ETMV3_EXC_PE_RESET = 8, 71 CS_ETMV3_EXC_UNDEFINED_INSTR = 9, 72 CS_ETMV3_EXC_SVC = 10, 73 CS_ETMV3_EXC_PREFETCH_ABORT = 11, 74 CS_ETMV3_EXC_DATA_FAULT = 12, 75 CS_ETMV3_EXC_GENERIC = 13, 76 CS_ETMV3_EXC_IRQ = 14, 77 CS_ETMV3_EXC_FIQ = 15, 78}; 79 80/* 81 * ETMv4 exception encoding number: 82 * See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D) 83 * table 6-12 Possible values for the TYPE field in an Exception instruction 84 * trace packet, for ARMv7-A/R and ARMv8-A/R PEs. 85 */ 86enum { 87 CS_ETMV4_EXC_RESET = 0, 88 CS_ETMV4_EXC_DEBUG_HALT = 1, 89 CS_ETMV4_EXC_CALL = 2, 90 CS_ETMV4_EXC_TRAP = 3, 91 CS_ETMV4_EXC_SYSTEM_ERROR = 4, 92 CS_ETMV4_EXC_INST_DEBUG = 6, 93 CS_ETMV4_EXC_DATA_DEBUG = 7, 94 CS_ETMV4_EXC_ALIGNMENT = 10, 95 CS_ETMV4_EXC_INST_FAULT = 11, 96 CS_ETMV4_EXC_DATA_FAULT = 12, 97 CS_ETMV4_EXC_IRQ = 14, 98 CS_ETMV4_EXC_FIQ = 15, 99 CS_ETMV4_EXC_END = 31, 100}; 101 102enum cs_etm_sample_type { 103 CS_ETM_EMPTY, 104 CS_ETM_RANGE, 105 CS_ETM_DISCONTINUITY, 106 CS_ETM_EXCEPTION, 107 CS_ETM_EXCEPTION_RET, 108}; 109 110enum cs_etm_isa { 111 CS_ETM_ISA_UNKNOWN, 112 CS_ETM_ISA_A64, 113 CS_ETM_ISA_A32, 114 CS_ETM_ISA_T32, 115}; 116 117struct cs_etm_queue; 118 119struct cs_etm_packet { 120 enum cs_etm_sample_type sample_type; 121 enum cs_etm_isa isa; 122 u64 start_addr; 123 u64 end_addr; 124 u32 instr_count; 125 u32 last_instr_type; 126 u32 last_instr_subtype; 127 u32 flags; 128 u32 exception_number; 129 u8 last_instr_cond; 130 u8 last_instr_taken_branch; 131 u8 last_instr_size; 132 u8 trace_chan_id; 133 int cpu; 134}; 135 136#define CS_ETM_PACKET_MAX_BUFFER 1024 137 138/* 139 * When working with per-thread scenarios the process under trace can 140 * be scheduled on any CPU and as such, more than one traceID may be 141 * associated with the same process. Since a traceID of '0' is illegal 142 * as per the CoreSight architecture, use that specific value to 143 * identify the queue where all packets (with any traceID) are 144 * aggregated. 145 */ 146#define CS_ETM_PER_THREAD_TRACEID 0 147 148struct cs_etm_packet_queue { 149 u32 packet_count; 150 u32 head; 151 u32 tail; 152 u32 instr_count; 153 u64 timestamp; 154 u64 next_timestamp; 155 struct cs_etm_packet packet_buffer[CS_ETM_PACKET_MAX_BUFFER]; 156}; 157 158#define KiB(x) ((x) * 1024) 159#define MiB(x) ((x) * 1024 * 1024) 160 161#define CS_ETM_INVAL_ADDR 0xdeadbeefdeadbeefUL 162 163#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) 164 165#define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_0_MAX * sizeof(u64)) 166 167#define __perf_cs_etmv3_magic 0x3030303030303030ULL 168#define __perf_cs_etmv4_magic 0x4040404040404040ULL 169#define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64)) 170#define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64)) 171 172#ifdef HAVE_CSTRACE_SUPPORT 173int cs_etm__process_auxtrace_info(union perf_event *event, 174 struct perf_session *session); 175int cs_etm__get_cpu(u8 trace_chan_id, int *cpu); 176int cs_etm__etmq_set_tid(struct cs_etm_queue *etmq, 177 pid_t tid, u8 trace_chan_id); 178bool cs_etm__etmq_is_timeless(struct cs_etm_queue *etmq); 179void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq, 180 u8 trace_chan_id); 181struct cs_etm_packet_queue 182*cs_etm__etmq_get_packet_queue(struct cs_etm_queue *etmq, u8 trace_chan_id); 183#else 184static inline int 185cs_etm__process_auxtrace_info(union perf_event *event __maybe_unused, 186 struct perf_session *session __maybe_unused) 187{ 188 return -1; 189} 190 191static inline int cs_etm__get_cpu(u8 trace_chan_id __maybe_unused, 192 int *cpu __maybe_unused) 193{ 194 return -1; 195} 196 197static inline int cs_etm__etmq_set_tid( 198 struct cs_etm_queue *etmq __maybe_unused, 199 pid_t tid __maybe_unused, 200 u8 trace_chan_id __maybe_unused) 201{ 202 return -1; 203} 204 205static inline bool cs_etm__etmq_is_timeless( 206 struct cs_etm_queue *etmq __maybe_unused) 207{ 208 /* What else to return? */ 209 return true; 210} 211 212static inline void cs_etm__etmq_set_traceid_queue_timestamp( 213 struct cs_etm_queue *etmq __maybe_unused, 214 u8 trace_chan_id __maybe_unused) {} 215 216static inline struct cs_etm_packet_queue *cs_etm__etmq_get_packet_queue( 217 struct cs_etm_queue *etmq __maybe_unused, 218 u8 trace_chan_id __maybe_unused) 219{ 220 return NULL; 221} 222#endif 223 224#endif 225