18c2ecf20Sopenharmony_ci[
28c2ecf20Sopenharmony_ci    {
38c2ecf20Sopenharmony_ci        "EventCode": "0x17",
48c2ecf20Sopenharmony_ci        "Counter": "0,1,2,3",
58c2ecf20Sopenharmony_ci        "UMask": "0x1",
68c2ecf20Sopenharmony_ci        "EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
78c2ecf20Sopenharmony_ci        "SampleAfterValue": "2000003",
88c2ecf20Sopenharmony_ci        "BriefDescription": "Valid instructions written to IQ per cycle.",
98c2ecf20Sopenharmony_ci        "CounterHTOff": "0,1,2,3,4,5,6,7"
108c2ecf20Sopenharmony_ci    },
118c2ecf20Sopenharmony_ci    {
128c2ecf20Sopenharmony_ci        "EventCode": "0x5C",
138c2ecf20Sopenharmony_ci        "Counter": "0,1,2,3",
148c2ecf20Sopenharmony_ci        "UMask": "0x1",
158c2ecf20Sopenharmony_ci        "EventName": "CPL_CYCLES.RING0",
168c2ecf20Sopenharmony_ci        "SampleAfterValue": "2000003",
178c2ecf20Sopenharmony_ci        "BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
188c2ecf20Sopenharmony_ci        "CounterHTOff": "0,1,2,3,4,5,6,7"
198c2ecf20Sopenharmony_ci    },
208c2ecf20Sopenharmony_ci    {
218c2ecf20Sopenharmony_ci        "EventCode": "0x5C",
228c2ecf20Sopenharmony_ci        "Counter": "0,1,2,3",
238c2ecf20Sopenharmony_ci        "UMask": "0x1",
248c2ecf20Sopenharmony_ci        "EdgeDetect": "1",
258c2ecf20Sopenharmony_ci        "EventName": "CPL_CYCLES.RING0_TRANS",
268c2ecf20Sopenharmony_ci        "SampleAfterValue": "100007",
278c2ecf20Sopenharmony_ci        "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
288c2ecf20Sopenharmony_ci        "CounterMask": "1",
298c2ecf20Sopenharmony_ci        "CounterHTOff": "0,1,2,3,4,5,6,7"
308c2ecf20Sopenharmony_ci    },
318c2ecf20Sopenharmony_ci    {
328c2ecf20Sopenharmony_ci        "EventCode": "0x5C",
338c2ecf20Sopenharmony_ci        "Counter": "0,1,2,3",
348c2ecf20Sopenharmony_ci        "UMask": "0x2",
358c2ecf20Sopenharmony_ci        "EventName": "CPL_CYCLES.RING123",
368c2ecf20Sopenharmony_ci        "SampleAfterValue": "2000003",
378c2ecf20Sopenharmony_ci        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
388c2ecf20Sopenharmony_ci        "CounterHTOff": "0,1,2,3,4,5,6,7"
398c2ecf20Sopenharmony_ci    },
408c2ecf20Sopenharmony_ci    {
418c2ecf20Sopenharmony_ci        "EventCode": "0x4E",
428c2ecf20Sopenharmony_ci        "Counter": "0,1,2,3",
438c2ecf20Sopenharmony_ci        "UMask": "0x2",
448c2ecf20Sopenharmony_ci        "EventName": "HW_PRE_REQ.DL1_MISS",
458c2ecf20Sopenharmony_ci        "SampleAfterValue": "2000003",
468c2ecf20Sopenharmony_ci        "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
478c2ecf20Sopenharmony_ci        "CounterHTOff": "0,1,2,3,4,5,6,7"
488c2ecf20Sopenharmony_ci    },
498c2ecf20Sopenharmony_ci    {
508c2ecf20Sopenharmony_ci        "EventCode": "0x63",
518c2ecf20Sopenharmony_ci        "Counter": "0,1,2,3",
528c2ecf20Sopenharmony_ci        "UMask": "0x1",
538c2ecf20Sopenharmony_ci        "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
548c2ecf20Sopenharmony_ci        "SampleAfterValue": "2000003",
558c2ecf20Sopenharmony_ci        "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
568c2ecf20Sopenharmony_ci        "CounterHTOff": "0,1,2,3,4,5,6,7"
578c2ecf20Sopenharmony_ci    }
588c2ecf20Sopenharmony_ci]