18c2ecf20Sopenharmony_ci[
28c2ecf20Sopenharmony_ci    {
38c2ecf20Sopenharmony_ci        "EventCode": "0x5C",
48c2ecf20Sopenharmony_ci        "UMask": "0x1",
58c2ecf20Sopenharmony_ci        "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
68c2ecf20Sopenharmony_ci        "Counter": "0,1,2,3",
78c2ecf20Sopenharmony_ci        "EventName": "CPL_CYCLES.RING0",
88c2ecf20Sopenharmony_ci        "PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
98c2ecf20Sopenharmony_ci        "SampleAfterValue": "2000003",
108c2ecf20Sopenharmony_ci        "CounterHTOff": "0,1,2,3,4,5,6,7"
118c2ecf20Sopenharmony_ci    },
128c2ecf20Sopenharmony_ci    {
138c2ecf20Sopenharmony_ci        "EdgeDetect": "1",
148c2ecf20Sopenharmony_ci        "EventCode": "0x5C",
158c2ecf20Sopenharmony_ci        "UMask": "0x1",
168c2ecf20Sopenharmony_ci        "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
178c2ecf20Sopenharmony_ci        "Counter": "0,1,2,3",
188c2ecf20Sopenharmony_ci        "EventName": "CPL_CYCLES.RING0_TRANS",
198c2ecf20Sopenharmony_ci        "CounterMask": "1",
208c2ecf20Sopenharmony_ci        "SampleAfterValue": "100003",
218c2ecf20Sopenharmony_ci        "CounterHTOff": "0,1,2,3,4,5,6,7"
228c2ecf20Sopenharmony_ci    },
238c2ecf20Sopenharmony_ci    {
248c2ecf20Sopenharmony_ci        "EventCode": "0x5C",
258c2ecf20Sopenharmony_ci        "UMask": "0x2",
268c2ecf20Sopenharmony_ci        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
278c2ecf20Sopenharmony_ci        "Counter": "0,1,2,3",
288c2ecf20Sopenharmony_ci        "EventName": "CPL_CYCLES.RING123",
298c2ecf20Sopenharmony_ci        "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
308c2ecf20Sopenharmony_ci        "SampleAfterValue": "2000003",
318c2ecf20Sopenharmony_ci        "CounterHTOff": "0,1,2,3,4,5,6,7"
328c2ecf20Sopenharmony_ci    },
338c2ecf20Sopenharmony_ci    {
348c2ecf20Sopenharmony_ci        "EventCode": "0x63",
358c2ecf20Sopenharmony_ci        "UMask": "0x1",
368c2ecf20Sopenharmony_ci        "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
378c2ecf20Sopenharmony_ci        "Counter": "0,1,2,3",
388c2ecf20Sopenharmony_ci        "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
398c2ecf20Sopenharmony_ci        "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
408c2ecf20Sopenharmony_ci        "SampleAfterValue": "2000003",
418c2ecf20Sopenharmony_ci        "CounterHTOff": "0,1,2,3,4,5,6,7"
428c2ecf20Sopenharmony_ci    }
438c2ecf20Sopenharmony_ci]