18c2ecf20Sopenharmony_ci[ 28c2ecf20Sopenharmony_ci { 38c2ecf20Sopenharmony_ci "EventCode": "0x5C", 48c2ecf20Sopenharmony_ci "UMask": "0x1", 58c2ecf20Sopenharmony_ci "BriefDescription": "Unhalted core cycles when the thread is in ring 0", 68c2ecf20Sopenharmony_ci "Counter": "0,1,2,3", 78c2ecf20Sopenharmony_ci "EventName": "CPL_CYCLES.RING0", 88c2ecf20Sopenharmony_ci "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", 98c2ecf20Sopenharmony_ci "SampleAfterValue": "2000003", 108c2ecf20Sopenharmony_ci "CounterHTOff": "0,1,2,3,4,5,6,7" 118c2ecf20Sopenharmony_ci }, 128c2ecf20Sopenharmony_ci { 138c2ecf20Sopenharmony_ci "EdgeDetect": "1", 148c2ecf20Sopenharmony_ci "EventCode": "0x5C", 158c2ecf20Sopenharmony_ci "UMask": "0x1", 168c2ecf20Sopenharmony_ci "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", 178c2ecf20Sopenharmony_ci "Counter": "0,1,2,3", 188c2ecf20Sopenharmony_ci "EventName": "CPL_CYCLES.RING0_TRANS", 198c2ecf20Sopenharmony_ci "CounterMask": "1", 208c2ecf20Sopenharmony_ci "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", 218c2ecf20Sopenharmony_ci "SampleAfterValue": "100007", 228c2ecf20Sopenharmony_ci "CounterHTOff": "0,1,2,3,4,5,6,7" 238c2ecf20Sopenharmony_ci }, 248c2ecf20Sopenharmony_ci { 258c2ecf20Sopenharmony_ci "EventCode": "0x5C", 268c2ecf20Sopenharmony_ci "UMask": "0x2", 278c2ecf20Sopenharmony_ci "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", 288c2ecf20Sopenharmony_ci "Counter": "0,1,2,3", 298c2ecf20Sopenharmony_ci "EventName": "CPL_CYCLES.RING123", 308c2ecf20Sopenharmony_ci "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", 318c2ecf20Sopenharmony_ci "SampleAfterValue": "2000003", 328c2ecf20Sopenharmony_ci "CounterHTOff": "0,1,2,3,4,5,6,7" 338c2ecf20Sopenharmony_ci }, 348c2ecf20Sopenharmony_ci { 358c2ecf20Sopenharmony_ci "EventCode": "0x63", 368c2ecf20Sopenharmony_ci "UMask": "0x1", 378c2ecf20Sopenharmony_ci "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", 388c2ecf20Sopenharmony_ci "Counter": "0,1,2,3", 398c2ecf20Sopenharmony_ci "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 408c2ecf20Sopenharmony_ci "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", 418c2ecf20Sopenharmony_ci "SampleAfterValue": "2000003", 428c2ecf20Sopenharmony_ci "CounterHTOff": "0,1,2,3,4,5,6,7" 438c2ecf20Sopenharmony_ci } 448c2ecf20Sopenharmony_ci]