1// SPDX-License-Identifier: GPL-2.0 2 3#include <string.h> 4 5#include "intel-pt-decoder/intel-pt-pkt-decoder.h" 6 7#include "debug.h" 8#include "tests/tests.h" 9#include "arch-tests.h" 10 11/** 12 * struct test_data - Test data. 13 * @len: number of bytes to decode 14 * @bytes: bytes to decode 15 * @ctx: packet context to decode 16 * @packet: expected packet 17 * @new_ctx: expected new packet context 18 * @ctx_unchanged: the packet context must not change 19 */ 20struct test_data { 21 int len; 22 u8 bytes[INTEL_PT_PKT_MAX_SZ]; 23 enum intel_pt_pkt_ctx ctx; 24 struct intel_pt_pkt packet; 25 enum intel_pt_pkt_ctx new_ctx; 26 int ctx_unchanged; 27} data[] = { 28 /* Padding Packet */ 29 {1, {0}, 0, {INTEL_PT_PAD, 0, 0}, 0, 1 }, 30 /* Short Taken/Not Taken Packet */ 31 {1, {4}, 0, {INTEL_PT_TNT, 1, 0}, 0, 0 }, 32 {1, {6}, 0, {INTEL_PT_TNT, 1, 0x20ULL << 58}, 0, 0 }, 33 {1, {0x80}, 0, {INTEL_PT_TNT, 6, 0}, 0, 0 }, 34 {1, {0xfe}, 0, {INTEL_PT_TNT, 6, 0x3fULL << 58}, 0, 0 }, 35 /* Long Taken/Not Taken Packet */ 36 {8, {0x02, 0xa3, 2}, 0, {INTEL_PT_TNT, 1, 0xa302ULL << 47}, 0, 0 }, 37 {8, {0x02, 0xa3, 3}, 0, {INTEL_PT_TNT, 1, 0x1a302ULL << 47}, 0, 0 }, 38 {8, {0x02, 0xa3, 0, 0, 0, 0, 0, 0x80}, 0, {INTEL_PT_TNT, 47, 0xa302ULL << 1}, 0, 0 }, 39 {8, {0x02, 0xa3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, 0, {INTEL_PT_TNT, 47, 0xffffffffffffa302ULL << 1}, 0, 0 }, 40 /* Target IP Packet */ 41 {1, {0x0d}, 0, {INTEL_PT_TIP, 0, 0}, 0, 0 }, 42 {3, {0x2d, 1, 2}, 0, {INTEL_PT_TIP, 1, 0x201}, 0, 0 }, 43 {5, {0x4d, 1, 2, 3, 4}, 0, {INTEL_PT_TIP, 2, 0x4030201}, 0, 0 }, 44 {7, {0x6d, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_TIP, 3, 0x60504030201}, 0, 0 }, 45 {7, {0x8d, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_TIP, 4, 0x60504030201}, 0, 0 }, 46 {9, {0xcd, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_TIP, 6, 0x807060504030201}, 0, 0 }, 47 /* Packet Generation Enable */ 48 {1, {0x11}, 0, {INTEL_PT_TIP_PGE, 0, 0}, 0, 0 }, 49 {3, {0x31, 1, 2}, 0, {INTEL_PT_TIP_PGE, 1, 0x201}, 0, 0 }, 50 {5, {0x51, 1, 2, 3, 4}, 0, {INTEL_PT_TIP_PGE, 2, 0x4030201}, 0, 0 }, 51 {7, {0x71, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_TIP_PGE, 3, 0x60504030201}, 0, 0 }, 52 {7, {0x91, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_TIP_PGE, 4, 0x60504030201}, 0, 0 }, 53 {9, {0xd1, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_TIP_PGE, 6, 0x807060504030201}, 0, 0 }, 54 /* Packet Generation Disable */ 55 {1, {0x01}, 0, {INTEL_PT_TIP_PGD, 0, 0}, 0, 0 }, 56 {3, {0x21, 1, 2}, 0, {INTEL_PT_TIP_PGD, 1, 0x201}, 0, 0 }, 57 {5, {0x41, 1, 2, 3, 4}, 0, {INTEL_PT_TIP_PGD, 2, 0x4030201}, 0, 0 }, 58 {7, {0x61, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_TIP_PGD, 3, 0x60504030201}, 0, 0 }, 59 {7, {0x81, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_TIP_PGD, 4, 0x60504030201}, 0, 0 }, 60 {9, {0xc1, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_TIP_PGD, 6, 0x807060504030201}, 0, 0 }, 61 /* Flow Update Packet */ 62 {1, {0x1d}, 0, {INTEL_PT_FUP, 0, 0}, 0, 0 }, 63 {3, {0x3d, 1, 2}, 0, {INTEL_PT_FUP, 1, 0x201}, 0, 0 }, 64 {5, {0x5d, 1, 2, 3, 4}, 0, {INTEL_PT_FUP, 2, 0x4030201}, 0, 0 }, 65 {7, {0x7d, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_FUP, 3, 0x60504030201}, 0, 0 }, 66 {7, {0x9d, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_FUP, 4, 0x60504030201}, 0, 0 }, 67 {9, {0xdd, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_FUP, 6, 0x807060504030201}, 0, 0 }, 68 /* Paging Information Packet */ 69 {8, {0x02, 0x43, 2, 4, 6, 8, 10, 12}, 0, {INTEL_PT_PIP, 0, 0x60504030201}, 0, 0 }, 70 {8, {0x02, 0x43, 3, 4, 6, 8, 10, 12}, 0, {INTEL_PT_PIP, 0, 0x60504030201 | (1ULL << 63)}, 0, 0 }, 71 /* Mode Exec Packet */ 72 {2, {0x99, 0x00}, 0, {INTEL_PT_MODE_EXEC, 0, 16}, 0, 0 }, 73 {2, {0x99, 0x01}, 0, {INTEL_PT_MODE_EXEC, 0, 64}, 0, 0 }, 74 {2, {0x99, 0x02}, 0, {INTEL_PT_MODE_EXEC, 0, 32}, 0, 0 }, 75 /* Mode TSX Packet */ 76 {2, {0x99, 0x20}, 0, {INTEL_PT_MODE_TSX, 0, 0}, 0, 0 }, 77 {2, {0x99, 0x21}, 0, {INTEL_PT_MODE_TSX, 0, 1}, 0, 0 }, 78 {2, {0x99, 0x22}, 0, {INTEL_PT_MODE_TSX, 0, 2}, 0, 0 }, 79 /* Trace Stop Packet */ 80 {2, {0x02, 0x83}, 0, {INTEL_PT_TRACESTOP, 0, 0}, 0, 0 }, 81 /* Core:Bus Ratio Packet */ 82 {4, {0x02, 0x03, 0x12, 0}, 0, {INTEL_PT_CBR, 0, 0x12}, 0, 1 }, 83 /* Timestamp Counter Packet */ 84 {8, {0x19, 1, 2, 3, 4, 5, 6, 7}, 0, {INTEL_PT_TSC, 0, 0x7060504030201}, 0, 1 }, 85 /* Mini Time Counter Packet */ 86 {2, {0x59, 0x12}, 0, {INTEL_PT_MTC, 0, 0x12}, 0, 1 }, 87 /* TSC / MTC Alignment Packet */ 88 {7, {0x02, 0x73}, 0, {INTEL_PT_TMA, 0, 0}, 0, 1 }, 89 {7, {0x02, 0x73, 1, 2}, 0, {INTEL_PT_TMA, 0, 0x201}, 0, 1 }, 90 {7, {0x02, 0x73, 0, 0, 0, 0xff, 1}, 0, {INTEL_PT_TMA, 0x1ff, 0}, 0, 1 }, 91 {7, {0x02, 0x73, 0x80, 0xc0, 0, 0xff, 1}, 0, {INTEL_PT_TMA, 0x1ff, 0xc080}, 0, 1 }, 92 /* Cycle Count Packet */ 93 {1, {0x03}, 0, {INTEL_PT_CYC, 0, 0}, 0, 1 }, 94 {1, {0x0b}, 0, {INTEL_PT_CYC, 0, 1}, 0, 1 }, 95 {1, {0xfb}, 0, {INTEL_PT_CYC, 0, 0x1f}, 0, 1 }, 96 {2, {0x07, 2}, 0, {INTEL_PT_CYC, 0, 0x20}, 0, 1 }, 97 {2, {0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0xfff}, 0, 1 }, 98 {3, {0x07, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x1000}, 0, 1 }, 99 {3, {0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0x7ffff}, 0, 1 }, 100 {4, {0x07, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x80000}, 0, 1 }, 101 {4, {0xff, 0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0x3ffffff}, 0, 1 }, 102 {5, {0x07, 1, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x4000000}, 0, 1 }, 103 {5, {0xff, 0xff, 0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0x1ffffffff}, 0, 1 }, 104 {6, {0x07, 1, 1, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x200000000}, 0, 1 }, 105 {6, {0xff, 0xff, 0xff, 0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0xffffffffff}, 0, 1 }, 106 {7, {0x07, 1, 1, 1, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x10000000000}, 0, 1 }, 107 {7, {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0x7fffffffffff}, 0, 1 }, 108 {8, {0x07, 1, 1, 1, 1, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x800000000000}, 0, 1 }, 109 {8, {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0x3fffffffffffff}, 0, 1 }, 110 {9, {0x07, 1, 1, 1, 1, 1, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x40000000000000}, 0, 1 }, 111 {9, {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0x1fffffffffffffff}, 0, 1 }, 112 {10, {0x07, 1, 1, 1, 1, 1, 1, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x2000000000000000}, 0, 1 }, 113 {10, {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe}, 0, {INTEL_PT_CYC, 0, 0xffffffffffffffff}, 0, 1 }, 114 /* Virtual-Machine Control Structure Packet */ 115 {7, {0x02, 0xc8, 1, 2, 3, 4, 5}, 0, {INTEL_PT_VMCS, 5, 0x504030201}, 0, 0 }, 116 /* Overflow Packet */ 117 {2, {0x02, 0xf3}, 0, {INTEL_PT_OVF, 0, 0}, 0, 0 }, 118 {2, {0x02, 0xf3}, INTEL_PT_BLK_4_CTX, {INTEL_PT_OVF, 0, 0}, 0, 0 }, 119 {2, {0x02, 0xf3}, INTEL_PT_BLK_8_CTX, {INTEL_PT_OVF, 0, 0}, 0, 0 }, 120 /* Packet Stream Boundary*/ 121 {16, {0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82}, 0, {INTEL_PT_PSB, 0, 0}, 0, 0 }, 122 {16, {0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82}, INTEL_PT_BLK_4_CTX, {INTEL_PT_PSB, 0, 0}, 0, 0 }, 123 {16, {0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82}, INTEL_PT_BLK_8_CTX, {INTEL_PT_PSB, 0, 0}, 0, 0 }, 124 /* PSB End Packet */ 125 {2, {0x02, 0x23}, 0, {INTEL_PT_PSBEND, 0, 0}, 0, 0 }, 126 /* Maintenance Packet */ 127 {11, {0x02, 0xc3, 0x88, 1, 2, 3, 4, 5, 6, 7}, 0, {INTEL_PT_MNT, 0, 0x7060504030201}, 0, 1 }, 128 /* Write Data to PT Packet */ 129 {6, {0x02, 0x12, 1, 2, 3, 4}, 0, {INTEL_PT_PTWRITE, 0, 0x4030201}, 0, 0 }, 130 {10, {0x02, 0x32, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_PTWRITE, 1, 0x807060504030201}, 0, 0 }, 131 {6, {0x02, 0x92, 1, 2, 3, 4}, 0, {INTEL_PT_PTWRITE_IP, 0, 0x4030201}, 0, 0 }, 132 {10, {0x02, 0xb2, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_PTWRITE_IP, 1, 0x807060504030201}, 0, 0 }, 133 /* Execution Stop Packet */ 134 {2, {0x02, 0x62}, 0, {INTEL_PT_EXSTOP, 0, 0}, 0, 1 }, 135 {2, {0x02, 0xe2}, 0, {INTEL_PT_EXSTOP_IP, 0, 0}, 0, 1 }, 136 /* Monitor Wait Packet */ 137 {10, {0x02, 0xc2}, 0, {INTEL_PT_MWAIT, 0, 0}, 0, 0 }, 138 {10, {0x02, 0xc2, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_MWAIT, 0, 0x807060504030201}, 0, 0 }, 139 {10, {0x02, 0xc2, 0xff, 2, 3, 4, 7, 6, 7, 8}, 0, {INTEL_PT_MWAIT, 0, 0x8070607040302ff}, 0, 0 }, 140 /* Power Entry Packet */ 141 {4, {0x02, 0x22}, 0, {INTEL_PT_PWRE, 0, 0}, 0, 1 }, 142 {4, {0x02, 0x22, 1, 2}, 0, {INTEL_PT_PWRE, 0, 0x0201}, 0, 1 }, 143 {4, {0x02, 0x22, 0x80, 0x34}, 0, {INTEL_PT_PWRE, 0, 0x3480}, 0, 1 }, 144 {4, {0x02, 0x22, 0x00, 0x56}, 0, {INTEL_PT_PWRE, 0, 0x5600}, 0, 1 }, 145 /* Power Exit Packet */ 146 {7, {0x02, 0xa2}, 0, {INTEL_PT_PWRX, 0, 0}, 0, 1 }, 147 {7, {0x02, 0xa2, 1, 2, 3, 4, 5}, 0, {INTEL_PT_PWRX, 0, 0x504030201}, 0, 1 }, 148 {7, {0x02, 0xa2, 0xff, 0xff, 0xff, 0xff, 0xff}, 0, {INTEL_PT_PWRX, 0, 0xffffffffff}, 0, 1 }, 149 /* Block Begin Packet */ 150 {3, {0x02, 0x63, 0x00}, 0, {INTEL_PT_BBP, 0, 0}, INTEL_PT_BLK_8_CTX, 0 }, 151 {3, {0x02, 0x63, 0x80}, 0, {INTEL_PT_BBP, 1, 0}, INTEL_PT_BLK_4_CTX, 0 }, 152 {3, {0x02, 0x63, 0x1f}, 0, {INTEL_PT_BBP, 0, 0x1f}, INTEL_PT_BLK_8_CTX, 0 }, 153 {3, {0x02, 0x63, 0x9f}, 0, {INTEL_PT_BBP, 1, 0x1f}, INTEL_PT_BLK_4_CTX, 0 }, 154 /* 4-byte Block Item Packet */ 155 {5, {0x04}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BIP, 0, 0}, INTEL_PT_BLK_4_CTX, 0 }, 156 {5, {0xfc}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BIP, 0x1f, 0}, INTEL_PT_BLK_4_CTX, 0 }, 157 {5, {0x04, 1, 2, 3, 4}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BIP, 0, 0x04030201}, INTEL_PT_BLK_4_CTX, 0 }, 158 {5, {0xfc, 1, 2, 3, 4}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BIP, 0x1f, 0x04030201}, INTEL_PT_BLK_4_CTX, 0 }, 159 /* 8-byte Block Item Packet */ 160 {9, {0x04}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BIP, 0, 0}, INTEL_PT_BLK_8_CTX, 0 }, 161 {9, {0xfc}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BIP, 0x1f, 0}, INTEL_PT_BLK_8_CTX, 0 }, 162 {9, {0x04, 1, 2, 3, 4, 5, 6, 7, 8}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BIP, 0, 0x0807060504030201}, INTEL_PT_BLK_8_CTX, 0 }, 163 {9, {0xfc, 1, 2, 3, 4, 5, 6, 7, 8}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BIP, 0x1f, 0x0807060504030201}, INTEL_PT_BLK_8_CTX, 0 }, 164 /* Block End Packet */ 165 {2, {0x02, 0x33}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BEP, 0, 0}, 0, 0 }, 166 {2, {0x02, 0xb3}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BEP_IP, 0, 0}, 0, 0 }, 167 {2, {0x02, 0x33}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BEP, 0, 0}, 0, 0 }, 168 {2, {0x02, 0xb3}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BEP_IP, 0, 0}, 0, 0 }, 169 /* Terminator */ 170 {0, {0}, 0, {0, 0, 0}, 0, 0 }, 171}; 172 173static int dump_packet(struct intel_pt_pkt *packet, u8 *bytes, int len) 174{ 175 char desc[INTEL_PT_PKT_DESC_MAX]; 176 int ret, i; 177 178 for (i = 0; i < len; i++) 179 pr_debug(" %02x", bytes[i]); 180 for (; i < INTEL_PT_PKT_MAX_SZ; i++) 181 pr_debug(" "); 182 pr_debug(" "); 183 ret = intel_pt_pkt_desc(packet, desc, INTEL_PT_PKT_DESC_MAX); 184 if (ret < 0) { 185 pr_debug("intel_pt_pkt_desc failed!\n"); 186 return TEST_FAIL; 187 } 188 pr_debug("%s\n", desc); 189 190 return TEST_OK; 191} 192 193static void decoding_failed(struct test_data *d) 194{ 195 pr_debug("Decoding failed!\n"); 196 pr_debug("Decoding: "); 197 dump_packet(&d->packet, d->bytes, d->len); 198} 199 200static int fail(struct test_data *d, struct intel_pt_pkt *packet, int len, 201 enum intel_pt_pkt_ctx new_ctx) 202{ 203 decoding_failed(d); 204 205 if (len != d->len) 206 pr_debug("Expected length: %d Decoded length %d\n", 207 d->len, len); 208 209 if (packet->type != d->packet.type) 210 pr_debug("Expected type: %d Decoded type %d\n", 211 d->packet.type, packet->type); 212 213 if (packet->count != d->packet.count) 214 pr_debug("Expected count: %d Decoded count %d\n", 215 d->packet.count, packet->count); 216 217 if (packet->payload != d->packet.payload) 218 pr_debug("Expected payload: 0x%llx Decoded payload 0x%llx\n", 219 (unsigned long long)d->packet.payload, 220 (unsigned long long)packet->payload); 221 222 if (new_ctx != d->new_ctx) 223 pr_debug("Expected packet context: %d Decoded packet context %d\n", 224 d->new_ctx, new_ctx); 225 226 return TEST_FAIL; 227} 228 229static int test_ctx_unchanged(struct test_data *d, struct intel_pt_pkt *packet, 230 enum intel_pt_pkt_ctx ctx) 231{ 232 enum intel_pt_pkt_ctx old_ctx = ctx; 233 234 intel_pt_upd_pkt_ctx(packet, &ctx); 235 236 if (ctx != old_ctx) { 237 decoding_failed(d); 238 pr_debug("Packet context changed!\n"); 239 return TEST_FAIL; 240 } 241 242 return TEST_OK; 243} 244 245static int test_one(struct test_data *d) 246{ 247 struct intel_pt_pkt packet; 248 enum intel_pt_pkt_ctx ctx = d->ctx; 249 int ret; 250 251 memset(&packet, 0xff, sizeof(packet)); 252 253 /* Decode a packet */ 254 ret = intel_pt_get_packet(d->bytes, d->len, &packet, &ctx); 255 if (ret < 0 || ret > INTEL_PT_PKT_MAX_SZ) { 256 decoding_failed(d); 257 pr_debug("intel_pt_get_packet returned %d\n", ret); 258 return TEST_FAIL; 259 } 260 261 /* Some packets must always leave the packet context unchanged */ 262 if (d->ctx_unchanged) { 263 int err; 264 265 err = test_ctx_unchanged(d, &packet, INTEL_PT_NO_CTX); 266 if (err) 267 return err; 268 err = test_ctx_unchanged(d, &packet, INTEL_PT_BLK_4_CTX); 269 if (err) 270 return err; 271 err = test_ctx_unchanged(d, &packet, INTEL_PT_BLK_8_CTX); 272 if (err) 273 return err; 274 } 275 276 /* Compare to the expected values */ 277 if (ret != d->len || packet.type != d->packet.type || 278 packet.count != d->packet.count || 279 packet.payload != d->packet.payload || ctx != d->new_ctx) 280 return fail(d, &packet, ret, ctx); 281 282 pr_debug("Decoded ok:"); 283 ret = dump_packet(&d->packet, d->bytes, d->len); 284 285 return ret; 286} 287 288/* 289 * This test feeds byte sequences to the Intel PT packet decoder and checks the 290 * results. Changes to the packet context are also checked. 291 */ 292int test__intel_pt_pkt_decoder(struct test *test __maybe_unused, int subtest __maybe_unused) 293{ 294 struct test_data *d = data; 295 int ret; 296 297 for (d = data; d->len; d++) { 298 ret = test_one(d); 299 if (ret) 300 return ret; 301 } 302 303 return TEST_OK; 304} 305