18c2ecf20Sopenharmony_ciC LB+fencembonceonce+ctrlonceonce 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ci(* 48c2ecf20Sopenharmony_ci * Result: Never 58c2ecf20Sopenharmony_ci * 68c2ecf20Sopenharmony_ci * This litmus test demonstrates that lightweight ordering suffices for 78c2ecf20Sopenharmony_ci * the load-buffering pattern, in other words, preventing all processes 88c2ecf20Sopenharmony_ci * reading from the preceding process's write. In this example, the 98c2ecf20Sopenharmony_ci * combination of a control dependency and a full memory barrier are enough 108c2ecf20Sopenharmony_ci * to do the trick. (But the full memory barrier could be replaced with 118c2ecf20Sopenharmony_ci * another control dependency and order would still be maintained.) 128c2ecf20Sopenharmony_ci *) 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci{} 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ciP0(int *x, int *y) 178c2ecf20Sopenharmony_ci{ 188c2ecf20Sopenharmony_ci int r0; 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ci r0 = READ_ONCE(*x); 218c2ecf20Sopenharmony_ci if (r0) 228c2ecf20Sopenharmony_ci WRITE_ONCE(*y, 1); 238c2ecf20Sopenharmony_ci} 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ciP1(int *x, int *y) 268c2ecf20Sopenharmony_ci{ 278c2ecf20Sopenharmony_ci int r0; 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci r0 = READ_ONCE(*y); 308c2ecf20Sopenharmony_ci smp_mb(); 318c2ecf20Sopenharmony_ci WRITE_ONCE(*x, 1); 328c2ecf20Sopenharmony_ci} 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ciexists (0:r0=1 /\ 1:r0=1) 35