1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_X86_MSR_INDEX_H 3#define _ASM_X86_MSR_INDEX_H 4 5#include <linux/bits.h> 6 7/* 8 * CPU model specific register (MSR) numbers. 9 * 10 * Do not add new entries to this file unless the definitions are shared 11 * between multiple compilation units. 12 */ 13 14/* x86-64 specific MSRs */ 15#define MSR_EFER 0xc0000080 /* extended feature register */ 16#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 17#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 18#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 19#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 20#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 21#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 22#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 23#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 24 25/* EFER bits: */ 26#define _EFER_SCE 0 /* SYSCALL/SYSRET */ 27#define _EFER_LME 8 /* Long mode enable */ 28#define _EFER_LMA 10 /* Long mode active (read-only) */ 29#define _EFER_NX 11 /* No execute enable */ 30#define _EFER_SVME 12 /* Enable virtualization */ 31#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 32#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 33 34#define EFER_SCE (1<<_EFER_SCE) 35#define EFER_LME (1<<_EFER_LME) 36#define EFER_LMA (1<<_EFER_LMA) 37#define EFER_NX (1<<_EFER_NX) 38#define EFER_SVME (1<<_EFER_SVME) 39#define EFER_LMSLE (1<<_EFER_LMSLE) 40#define EFER_FFXSR (1<<_EFER_FFXSR) 41 42/* Intel MSRs. Some also available on other CPUs */ 43 44#define MSR_TEST_CTRL 0x00000033 45#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 46#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) 47 48#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 49#define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 50#define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 51#define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 52#define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 53#define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 54#define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ 55#define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) 56 57#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 58#define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 59 60#define MSR_PPIN_CTL 0x0000004e 61#define MSR_PPIN 0x0000004f 62 63#define MSR_IA32_PERFCTR0 0x000000c1 64#define MSR_IA32_PERFCTR1 0x000000c2 65#define MSR_FSB_FREQ 0x000000cd 66#define MSR_PLATFORM_INFO 0x000000ce 67#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 68#define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 69 70#define MSR_IA32_UMWAIT_CONTROL 0xe1 71#define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 72#define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 73/* 74 * The time field is bit[31:2], but representing a 32bit value with 75 * bit[1:0] zero. 76 */ 77#define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 78 79/* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ 80#define MSR_IA32_CORE_CAPS 0x000000cf 81#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 82#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) 83 84#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 85#define NHM_C3_AUTO_DEMOTE (1UL << 25) 86#define NHM_C1_AUTO_DEMOTE (1UL << 26) 87#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 88#define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 89#define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 90 91#define MSR_MTRRcap 0x000000fe 92 93#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 94#define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 95#define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 96#define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */ 97#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 98#define ARCH_CAP_SSB_NO BIT(4) /* 99 * Not susceptible to Speculative Store Bypass 100 * attack, so no Speculative Store Bypass 101 * control required. 102 */ 103#define ARCH_CAP_MDS_NO BIT(5) /* 104 * Not susceptible to 105 * Microarchitectural Data 106 * Sampling (MDS) vulnerabilities. 107 */ 108#define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 109 * The processor is not susceptible to a 110 * machine check error due to modifying the 111 * code page size along with either the 112 * physical address or cache type 113 * without TLB invalidation. 114 */ 115#define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 116#define ARCH_CAP_TAA_NO BIT(8) /* 117 * Not susceptible to 118 * TSX Async Abort (TAA) vulnerabilities. 119 */ 120#define ARCH_CAP_SBDR_SSDP_NO BIT(13) /* 121 * Not susceptible to SBDR and SSDP 122 * variants of Processor MMIO stale data 123 * vulnerabilities. 124 */ 125#define ARCH_CAP_FBSDP_NO BIT(14) /* 126 * Not susceptible to FBSDP variant of 127 * Processor MMIO stale data 128 * vulnerabilities. 129 */ 130#define ARCH_CAP_PSDP_NO BIT(15) /* 131 * Not susceptible to PSDP variant of 132 * Processor MMIO stale data 133 * vulnerabilities. 134 */ 135#define ARCH_CAP_FB_CLEAR BIT(17) /* 136 * VERW clears CPU fill buffer 137 * even on MDS_NO CPUs. 138 */ 139#define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /* 140 * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS] 141 * bit available to control VERW 142 * behavior. 143 */ 144#define ARCH_CAP_RRSBA BIT(19) /* 145 * Indicates RET may use predictors 146 * other than the RSB. With eIBRS 147 * enabled predictions in kernel mode 148 * are restricted to targets in 149 * kernel. 150 */ 151#define ARCH_CAP_PBRSB_NO BIT(24) /* 152 * Not susceptible to Post-Barrier 153 * Return Stack Buffer Predictions. 154 */ 155 156#define MSR_IA32_FLUSH_CMD 0x0000010b 157#define L1D_FLUSH BIT(0) /* 158 * Writeback and invalidate the 159 * L1 data cache. 160 */ 161 162#define MSR_IA32_BBL_CR_CTL 0x00000119 163#define MSR_IA32_BBL_CR_CTL3 0x0000011e 164 165#define MSR_IA32_TSX_CTRL 0x00000122 166#define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 167#define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 168 169/* SRBDS support */ 170#define MSR_IA32_MCU_OPT_CTRL 0x00000123 171#define RNGDS_MITG_DIS BIT(0) 172#define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ 173 174#define MSR_IA32_SYSENTER_CS 0x00000174 175#define MSR_IA32_SYSENTER_ESP 0x00000175 176#define MSR_IA32_SYSENTER_EIP 0x00000176 177 178#define MSR_IA32_MCG_CAP 0x00000179 179#define MSR_IA32_MCG_STATUS 0x0000017a 180#define MSR_IA32_MCG_CTL 0x0000017b 181#define MSR_IA32_MCG_EXT_CTL 0x000004d0 182 183#define MSR_OFFCORE_RSP_0 0x000001a6 184#define MSR_OFFCORE_RSP_1 0x000001a7 185#define MSR_TURBO_RATIO_LIMIT 0x000001ad 186#define MSR_TURBO_RATIO_LIMIT1 0x000001ae 187#define MSR_TURBO_RATIO_LIMIT2 0x000001af 188 189#define MSR_LBR_SELECT 0x000001c8 190#define MSR_LBR_TOS 0x000001c9 191 192#define MSR_IA32_POWER_CTL 0x000001fc 193#define MSR_IA32_POWER_CTL_BIT_EE 19 194 195#define MSR_LBR_NHM_FROM 0x00000680 196#define MSR_LBR_NHM_TO 0x000006c0 197#define MSR_LBR_CORE_FROM 0x00000040 198#define MSR_LBR_CORE_TO 0x00000060 199 200#define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 201#define LBR_INFO_MISPRED BIT_ULL(63) 202#define LBR_INFO_IN_TX BIT_ULL(62) 203#define LBR_INFO_ABORT BIT_ULL(61) 204#define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) 205#define LBR_INFO_CYCLES 0xffff 206#define LBR_INFO_BR_TYPE_OFFSET 56 207#define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) 208 209#define MSR_ARCH_LBR_CTL 0x000014ce 210#define ARCH_LBR_CTL_LBREN BIT(0) 211#define ARCH_LBR_CTL_CPL_OFFSET 1 212#define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) 213#define ARCH_LBR_CTL_STACK_OFFSET 3 214#define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) 215#define ARCH_LBR_CTL_FILTER_OFFSET 16 216#define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) 217#define MSR_ARCH_LBR_DEPTH 0x000014cf 218#define MSR_ARCH_LBR_FROM_0 0x00001500 219#define MSR_ARCH_LBR_TO_0 0x00001600 220#define MSR_ARCH_LBR_INFO_0 0x00001200 221 222#define MSR_IA32_PEBS_ENABLE 0x000003f1 223#define MSR_PEBS_DATA_CFG 0x000003f2 224#define MSR_IA32_DS_AREA 0x00000600 225#define MSR_IA32_PERF_CAPABILITIES 0x00000345 226#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 227 228#define MSR_IA32_RTIT_CTL 0x00000570 229#define RTIT_CTL_TRACEEN BIT(0) 230#define RTIT_CTL_CYCLEACC BIT(1) 231#define RTIT_CTL_OS BIT(2) 232#define RTIT_CTL_USR BIT(3) 233#define RTIT_CTL_PWR_EVT_EN BIT(4) 234#define RTIT_CTL_FUP_ON_PTW BIT(5) 235#define RTIT_CTL_FABRIC_EN BIT(6) 236#define RTIT_CTL_CR3EN BIT(7) 237#define RTIT_CTL_TOPA BIT(8) 238#define RTIT_CTL_MTC_EN BIT(9) 239#define RTIT_CTL_TSC_EN BIT(10) 240#define RTIT_CTL_DISRETC BIT(11) 241#define RTIT_CTL_PTW_EN BIT(12) 242#define RTIT_CTL_BRANCH_EN BIT(13) 243#define RTIT_CTL_MTC_RANGE_OFFSET 14 244#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 245#define RTIT_CTL_CYC_THRESH_OFFSET 19 246#define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 247#define RTIT_CTL_PSB_FREQ_OFFSET 24 248#define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 249#define RTIT_CTL_ADDR0_OFFSET 32 250#define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 251#define RTIT_CTL_ADDR1_OFFSET 36 252#define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 253#define RTIT_CTL_ADDR2_OFFSET 40 254#define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 255#define RTIT_CTL_ADDR3_OFFSET 44 256#define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 257#define MSR_IA32_RTIT_STATUS 0x00000571 258#define RTIT_STATUS_FILTEREN BIT(0) 259#define RTIT_STATUS_CONTEXTEN BIT(1) 260#define RTIT_STATUS_TRIGGEREN BIT(2) 261#define RTIT_STATUS_BUFFOVF BIT(3) 262#define RTIT_STATUS_ERROR BIT(4) 263#define RTIT_STATUS_STOPPED BIT(5) 264#define RTIT_STATUS_BYTECNT_OFFSET 32 265#define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 266#define MSR_IA32_RTIT_ADDR0_A 0x00000580 267#define MSR_IA32_RTIT_ADDR0_B 0x00000581 268#define MSR_IA32_RTIT_ADDR1_A 0x00000582 269#define MSR_IA32_RTIT_ADDR1_B 0x00000583 270#define MSR_IA32_RTIT_ADDR2_A 0x00000584 271#define MSR_IA32_RTIT_ADDR2_B 0x00000585 272#define MSR_IA32_RTIT_ADDR3_A 0x00000586 273#define MSR_IA32_RTIT_ADDR3_B 0x00000587 274#define MSR_IA32_RTIT_CR3_MATCH 0x00000572 275#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 276#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 277 278#define MSR_MTRRfix64K_00000 0x00000250 279#define MSR_MTRRfix16K_80000 0x00000258 280#define MSR_MTRRfix16K_A0000 0x00000259 281#define MSR_MTRRfix4K_C0000 0x00000268 282#define MSR_MTRRfix4K_C8000 0x00000269 283#define MSR_MTRRfix4K_D0000 0x0000026a 284#define MSR_MTRRfix4K_D8000 0x0000026b 285#define MSR_MTRRfix4K_E0000 0x0000026c 286#define MSR_MTRRfix4K_E8000 0x0000026d 287#define MSR_MTRRfix4K_F0000 0x0000026e 288#define MSR_MTRRfix4K_F8000 0x0000026f 289#define MSR_MTRRdefType 0x000002ff 290 291#define MSR_IA32_CR_PAT 0x00000277 292 293#define MSR_IA32_DEBUGCTLMSR 0x000001d9 294#define MSR_IA32_LASTBRANCHFROMIP 0x000001db 295#define MSR_IA32_LASTBRANCHTOIP 0x000001dc 296#define MSR_IA32_LASTINTFROMIP 0x000001dd 297#define MSR_IA32_LASTINTTOIP 0x000001de 298 299#define MSR_IA32_PASID 0x00000d93 300#define MSR_IA32_PASID_VALID BIT_ULL(31) 301 302/* DEBUGCTLMSR bits (others vary by model): */ 303#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 304#define DEBUGCTLMSR_BTF_SHIFT 1 305#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 306#define DEBUGCTLMSR_TR (1UL << 6) 307#define DEBUGCTLMSR_BTS (1UL << 7) 308#define DEBUGCTLMSR_BTINT (1UL << 8) 309#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 310#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 311#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 312#define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 313#define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 314#define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 315 316#define MSR_PEBS_FRONTEND 0x000003f7 317 318#define MSR_IA32_MC0_CTL 0x00000400 319#define MSR_IA32_MC0_STATUS 0x00000401 320#define MSR_IA32_MC0_ADDR 0x00000402 321#define MSR_IA32_MC0_MISC 0x00000403 322 323/* C-state Residency Counters */ 324#define MSR_PKG_C3_RESIDENCY 0x000003f8 325#define MSR_PKG_C6_RESIDENCY 0x000003f9 326#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 327#define MSR_PKG_C7_RESIDENCY 0x000003fa 328#define MSR_CORE_C3_RESIDENCY 0x000003fc 329#define MSR_CORE_C6_RESIDENCY 0x000003fd 330#define MSR_CORE_C7_RESIDENCY 0x000003fe 331#define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 332#define MSR_PKG_C2_RESIDENCY 0x0000060d 333#define MSR_PKG_C8_RESIDENCY 0x00000630 334#define MSR_PKG_C9_RESIDENCY 0x00000631 335#define MSR_PKG_C10_RESIDENCY 0x00000632 336 337/* Interrupt Response Limit */ 338#define MSR_PKGC3_IRTL 0x0000060a 339#define MSR_PKGC6_IRTL 0x0000060b 340#define MSR_PKGC7_IRTL 0x0000060c 341#define MSR_PKGC8_IRTL 0x00000633 342#define MSR_PKGC9_IRTL 0x00000634 343#define MSR_PKGC10_IRTL 0x00000635 344 345/* Run Time Average Power Limiting (RAPL) Interface */ 346 347#define MSR_RAPL_POWER_UNIT 0x00000606 348 349#define MSR_PKG_POWER_LIMIT 0x00000610 350#define MSR_PKG_ENERGY_STATUS 0x00000611 351#define MSR_PKG_PERF_STATUS 0x00000613 352#define MSR_PKG_POWER_INFO 0x00000614 353 354#define MSR_DRAM_POWER_LIMIT 0x00000618 355#define MSR_DRAM_ENERGY_STATUS 0x00000619 356#define MSR_DRAM_PERF_STATUS 0x0000061b 357#define MSR_DRAM_POWER_INFO 0x0000061c 358 359#define MSR_PP0_POWER_LIMIT 0x00000638 360#define MSR_PP0_ENERGY_STATUS 0x00000639 361#define MSR_PP0_POLICY 0x0000063a 362#define MSR_PP0_PERF_STATUS 0x0000063b 363 364#define MSR_PP1_POWER_LIMIT 0x00000640 365#define MSR_PP1_ENERGY_STATUS 0x00000641 366#define MSR_PP1_POLICY 0x00000642 367 368#define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b 369#define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 370 371/* Config TDP MSRs */ 372#define MSR_CONFIG_TDP_NOMINAL 0x00000648 373#define MSR_CONFIG_TDP_LEVEL_1 0x00000649 374#define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 375#define MSR_CONFIG_TDP_CONTROL 0x0000064B 376#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 377 378#define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 379 380#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 381#define MSR_PKG_ANY_CORE_C0_RES 0x00000659 382#define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 383#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 384 385#define MSR_CORE_C1_RES 0x00000660 386#define MSR_MODULE_C6_RES_MS 0x00000664 387 388#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 389#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 390 391#define MSR_ATOM_CORE_RATIOS 0x0000066a 392#define MSR_ATOM_CORE_VIDS 0x0000066b 393#define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 394#define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 395 396 397#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 398#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 399#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 400 401/* Hardware P state interface */ 402#define MSR_PPERF 0x0000064e 403#define MSR_PERF_LIMIT_REASONS 0x0000064f 404#define MSR_PM_ENABLE 0x00000770 405#define MSR_HWP_CAPABILITIES 0x00000771 406#define MSR_HWP_REQUEST_PKG 0x00000772 407#define MSR_HWP_INTERRUPT 0x00000773 408#define MSR_HWP_REQUEST 0x00000774 409#define MSR_HWP_STATUS 0x00000777 410 411/* CPUID.6.EAX */ 412#define HWP_BASE_BIT (1<<7) 413#define HWP_NOTIFICATIONS_BIT (1<<8) 414#define HWP_ACTIVITY_WINDOW_BIT (1<<9) 415#define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 416#define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 417 418/* IA32_HWP_CAPABILITIES */ 419#define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 420#define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 421#define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 422#define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 423 424/* IA32_HWP_REQUEST */ 425#define HWP_MIN_PERF(x) (x & 0xff) 426#define HWP_MAX_PERF(x) ((x & 0xff) << 8) 427#define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 428#define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 429#define HWP_EPP_PERFORMANCE 0x00 430#define HWP_EPP_BALANCE_PERFORMANCE 0x80 431#define HWP_EPP_BALANCE_POWERSAVE 0xC0 432#define HWP_EPP_POWERSAVE 0xFF 433#define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 434#define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 435 436/* IA32_HWP_STATUS */ 437#define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 438#define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 439 440/* IA32_HWP_INTERRUPT */ 441#define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 442#define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 443 444#define MSR_AMD64_MC0_MASK 0xc0010044 445 446#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 447#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 448#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 449#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 450 451#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 452 453/* These are consecutive and not in the normal 4er MCE bank block */ 454#define MSR_IA32_MC0_CTL2 0x00000280 455#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 456 457#define MSR_P6_PERFCTR0 0x000000c1 458#define MSR_P6_PERFCTR1 0x000000c2 459#define MSR_P6_EVNTSEL0 0x00000186 460#define MSR_P6_EVNTSEL1 0x00000187 461 462#define MSR_KNC_PERFCTR0 0x00000020 463#define MSR_KNC_PERFCTR1 0x00000021 464#define MSR_KNC_EVNTSEL0 0x00000028 465#define MSR_KNC_EVNTSEL1 0x00000029 466 467/* Alternative perfctr range with full access. */ 468#define MSR_IA32_PMC0 0x000004c1 469 470/* Auto-reload via MSR instead of DS area */ 471#define MSR_RELOAD_PMC0 0x000014c1 472#define MSR_RELOAD_FIXED_CTR0 0x00001309 473 474/* 475 * AMD64 MSRs. Not complete. See the architecture manual for a more 476 * complete list. 477 */ 478#define MSR_AMD64_PATCH_LEVEL 0x0000008b 479#define MSR_AMD64_TSC_RATIO 0xc0000104 480#define MSR_AMD64_NB_CFG 0xc001001f 481#define MSR_AMD64_PATCH_LOADER 0xc0010020 482#define MSR_AMD_PERF_CTL 0xc0010062 483#define MSR_AMD_PERF_STATUS 0xc0010063 484#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 485#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 486#define MSR_AMD64_OSVW_STATUS 0xc0010141 487#define MSR_AMD_PPIN_CTL 0xc00102f0 488#define MSR_AMD_PPIN 0xc00102f1 489#define MSR_AMD64_CPUID_FN_1 0xc0011004 490#define MSR_AMD64_LS_CFG 0xc0011020 491#define MSR_AMD64_DC_CFG 0xc0011022 492 493#define MSR_AMD64_DE_CFG 0xc0011029 494#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1 495#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT) 496 497#define MSR_AMD64_BU_CFG2 0xc001102a 498#define MSR_AMD64_IBSFETCHCTL 0xc0011030 499#define MSR_AMD64_IBSFETCHLINAD 0xc0011031 500#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 501#define MSR_AMD64_IBSFETCH_REG_COUNT 3 502#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 503#define MSR_AMD64_IBSOPCTL 0xc0011033 504#define MSR_AMD64_IBSOPRIP 0xc0011034 505#define MSR_AMD64_IBSOPDATA 0xc0011035 506#define MSR_AMD64_IBSOPDATA2 0xc0011036 507#define MSR_AMD64_IBSOPDATA3 0xc0011037 508#define MSR_AMD64_IBSDCLINAD 0xc0011038 509#define MSR_AMD64_IBSDCPHYSAD 0xc0011039 510#define MSR_AMD64_IBSOP_REG_COUNT 7 511#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 512#define MSR_AMD64_IBSCTL 0xc001103a 513#define MSR_AMD64_IBSBRTARGET 0xc001103b 514#define MSR_AMD64_ICIBSEXTDCTL 0xc001103c 515#define MSR_AMD64_IBSOPDATA4 0xc001103d 516#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 517#define MSR_AMD64_SEV_ES_GHCB 0xc0010130 518#define MSR_AMD64_SEV 0xc0010131 519#define MSR_AMD64_SEV_ENABLED_BIT 0 520#define MSR_AMD64_SEV_ES_ENABLED_BIT 1 521#define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 522#define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) 523 524#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 525 526/* Fam 17h MSRs */ 527#define MSR_F17H_IRPERF 0xc00000e9 528 529#define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 530#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) 531 532/* Fam 16h MSRs */ 533#define MSR_F16H_L2I_PERF_CTL 0xc0010230 534#define MSR_F16H_L2I_PERF_CTR 0xc0010231 535#define MSR_F16H_DR1_ADDR_MASK 0xc0011019 536#define MSR_F16H_DR2_ADDR_MASK 0xc001101a 537#define MSR_F16H_DR3_ADDR_MASK 0xc001101b 538#define MSR_F16H_DR0_ADDR_MASK 0xc0011027 539 540/* Fam 15h MSRs */ 541#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a 542#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b 543#define MSR_F15H_PERF_CTL 0xc0010200 544#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 545#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 546#define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 547#define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 548#define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 549#define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 550 551#define MSR_F15H_PERF_CTR 0xc0010201 552#define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 553#define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 554#define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 555#define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 556#define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 557#define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 558 559#define MSR_F15H_NB_PERF_CTL 0xc0010240 560#define MSR_F15H_NB_PERF_CTR 0xc0010241 561#define MSR_F15H_PTSC 0xc0010280 562#define MSR_F15H_IC_CFG 0xc0011021 563#define MSR_F15H_EX_CFG 0xc001102c 564 565/* Fam 10h MSRs */ 566#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 567#define FAM10H_MMIO_CONF_ENABLE (1<<0) 568#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 569#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 570#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 571#define FAM10H_MMIO_CONF_BASE_SHIFT 20 572#define MSR_FAM10H_NODE_ID 0xc001100c 573 574/* K8 MSRs */ 575#define MSR_K8_TOP_MEM1 0xc001001a 576#define MSR_K8_TOP_MEM2 0xc001001d 577#define MSR_K8_SYSCFG 0xc0010010 578#define MSR_K8_SYSCFG_MEM_ENCRYPT_BIT 23 579#define MSR_K8_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_K8_SYSCFG_MEM_ENCRYPT_BIT) 580#define MSR_K8_INT_PENDING_MSG 0xc0010055 581/* C1E active bits in int pending message */ 582#define K8_INTP_C1E_ACTIVE_MASK 0x18000000 583#define MSR_K8_TSEG_ADDR 0xc0010112 584#define MSR_K8_TSEG_MASK 0xc0010113 585#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 586#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 587#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 588 589/* K7 MSRs */ 590#define MSR_K7_EVNTSEL0 0xc0010000 591#define MSR_K7_PERFCTR0 0xc0010004 592#define MSR_K7_EVNTSEL1 0xc0010001 593#define MSR_K7_PERFCTR1 0xc0010005 594#define MSR_K7_EVNTSEL2 0xc0010002 595#define MSR_K7_PERFCTR2 0xc0010006 596#define MSR_K7_EVNTSEL3 0xc0010003 597#define MSR_K7_PERFCTR3 0xc0010007 598#define MSR_K7_CLK_CTL 0xc001001b 599#define MSR_K7_HWCR 0xc0010015 600#define MSR_K7_HWCR_SMMLOCK_BIT 0 601#define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 602#define MSR_K7_HWCR_IRPERF_EN_BIT 30 603#define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) 604#define MSR_K7_FID_VID_CTL 0xc0010041 605#define MSR_K7_FID_VID_STATUS 0xc0010042 606 607/* K6 MSRs */ 608#define MSR_K6_WHCR 0xc0000082 609#define MSR_K6_UWCCR 0xc0000085 610#define MSR_K6_EPMR 0xc0000086 611#define MSR_K6_PSOR 0xc0000087 612#define MSR_K6_PFIR 0xc0000088 613 614/* Centaur-Hauls/IDT defined MSRs. */ 615#define MSR_IDT_FCR1 0x00000107 616#define MSR_IDT_FCR2 0x00000108 617#define MSR_IDT_FCR3 0x00000109 618#define MSR_IDT_FCR4 0x0000010a 619 620#define MSR_IDT_MCR0 0x00000110 621#define MSR_IDT_MCR1 0x00000111 622#define MSR_IDT_MCR2 0x00000112 623#define MSR_IDT_MCR3 0x00000113 624#define MSR_IDT_MCR4 0x00000114 625#define MSR_IDT_MCR5 0x00000115 626#define MSR_IDT_MCR6 0x00000116 627#define MSR_IDT_MCR7 0x00000117 628#define MSR_IDT_MCR_CTRL 0x00000120 629 630/* VIA Cyrix defined MSRs*/ 631#define MSR_VIA_FCR 0x00001107 632#define MSR_VIA_LONGHAUL 0x0000110a 633#define MSR_VIA_RNG 0x0000110b 634#define MSR_VIA_BCR2 0x00001147 635 636/* Transmeta defined MSRs */ 637#define MSR_TMTA_LONGRUN_CTRL 0x80868010 638#define MSR_TMTA_LONGRUN_FLAGS 0x80868011 639#define MSR_TMTA_LRTI_READOUT 0x80868018 640#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 641 642/* Intel defined MSRs. */ 643#define MSR_IA32_P5_MC_ADDR 0x00000000 644#define MSR_IA32_P5_MC_TYPE 0x00000001 645#define MSR_IA32_TSC 0x00000010 646#define MSR_IA32_PLATFORM_ID 0x00000017 647#define MSR_IA32_EBL_CR_POWERON 0x0000002a 648#define MSR_EBC_FREQUENCY_ID 0x0000002c 649#define MSR_SMI_COUNT 0x00000034 650 651/* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ 652#define MSR_IA32_FEAT_CTL 0x0000003a 653#define FEAT_CTL_LOCKED BIT(0) 654#define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) 655#define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) 656#define FEAT_CTL_LMCE_ENABLED BIT(20) 657 658#define MSR_IA32_TSC_ADJUST 0x0000003b 659#define MSR_IA32_BNDCFGS 0x00000d90 660 661#define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 662 663#define MSR_IA32_XSS 0x00000da0 664 665#define MSR_IA32_APICBASE 0x0000001b 666#define MSR_IA32_APICBASE_BSP (1<<8) 667#define MSR_IA32_APICBASE_ENABLE (1<<11) 668#define MSR_IA32_APICBASE_BASE (0xfffff<<12) 669 670#define MSR_IA32_TSCDEADLINE 0x000006e0 671 672#define MSR_IA32_UCODE_WRITE 0x00000079 673#define MSR_IA32_UCODE_REV 0x0000008b 674 675#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 676#define MSR_IA32_SMBASE 0x0000009e 677 678#define MSR_IA32_PERF_STATUS 0x00000198 679#define MSR_IA32_PERF_CTL 0x00000199 680#define INTEL_PERF_CTL_MASK 0xffff 681 682#define MSR_IA32_MPERF 0x000000e7 683#define MSR_IA32_APERF 0x000000e8 684 685#define MSR_IA32_THERM_CONTROL 0x0000019a 686#define MSR_IA32_THERM_INTERRUPT 0x0000019b 687 688#define THERM_INT_HIGH_ENABLE (1 << 0) 689#define THERM_INT_LOW_ENABLE (1 << 1) 690#define THERM_INT_PLN_ENABLE (1 << 24) 691 692#define MSR_IA32_THERM_STATUS 0x0000019c 693 694#define THERM_STATUS_PROCHOT (1 << 0) 695#define THERM_STATUS_POWER_LIMIT (1 << 10) 696 697#define MSR_THERM2_CTL 0x0000019d 698 699#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 700 701#define MSR_IA32_MISC_ENABLE 0x000001a0 702 703#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 704 705#define MSR_MISC_FEATURE_CONTROL 0x000001a4 706#define MSR_MISC_PWR_MGMT 0x000001aa 707 708#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 709#define ENERGY_PERF_BIAS_PERFORMANCE 0 710#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 711#define ENERGY_PERF_BIAS_NORMAL 6 712#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 713#define ENERGY_PERF_BIAS_POWERSAVE 15 714 715#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 716 717#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 718#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 719 720#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 721 722#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 723#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 724#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 725 726/* Thermal Thresholds Support */ 727#define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 728#define THERM_SHIFT_THRESHOLD0 8 729#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 730#define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 731#define THERM_SHIFT_THRESHOLD1 16 732#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 733#define THERM_STATUS_THRESHOLD0 (1 << 6) 734#define THERM_LOG_THRESHOLD0 (1 << 7) 735#define THERM_STATUS_THRESHOLD1 (1 << 8) 736#define THERM_LOG_THRESHOLD1 (1 << 9) 737 738/* MISC_ENABLE bits: architectural */ 739#define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 740#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 741#define MSR_IA32_MISC_ENABLE_TCC_BIT 1 742#define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 743#define MSR_IA32_MISC_ENABLE_EMON_BIT 7 744#define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 745#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 746#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 747#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 748#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 749#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 750#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 751#define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 752#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 753#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 754#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 755#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 756#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 757#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 758#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 759 760/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 761#define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 762#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 763#define MSR_IA32_MISC_ENABLE_TM1_BIT 3 764#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 765#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 766#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 767#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 768#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 769#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 770#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 771#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 772#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 773#define MSR_IA32_MISC_ENABLE_FERR_BIT 10 774#define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 775#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 776#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 777#define MSR_IA32_MISC_ENABLE_TM2_BIT 13 778#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 779#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 780#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 781#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 782#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 783#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 784#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 785#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 786#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 787#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 788#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 789#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 790#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 791 792/* MISC_FEATURES_ENABLES non-architectural features */ 793#define MSR_MISC_FEATURES_ENABLES 0x00000140 794 795#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 796#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 797#define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 798 799#define MSR_IA32_TSC_DEADLINE 0x000006E0 800 801 802#define MSR_TSX_FORCE_ABORT 0x0000010F 803 804#define MSR_TFA_RTM_FORCE_ABORT_BIT 0 805#define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 806 807/* P4/Xeon+ specific */ 808#define MSR_IA32_MCG_EAX 0x00000180 809#define MSR_IA32_MCG_EBX 0x00000181 810#define MSR_IA32_MCG_ECX 0x00000182 811#define MSR_IA32_MCG_EDX 0x00000183 812#define MSR_IA32_MCG_ESI 0x00000184 813#define MSR_IA32_MCG_EDI 0x00000185 814#define MSR_IA32_MCG_EBP 0x00000186 815#define MSR_IA32_MCG_ESP 0x00000187 816#define MSR_IA32_MCG_EFLAGS 0x00000188 817#define MSR_IA32_MCG_EIP 0x00000189 818#define MSR_IA32_MCG_RESERVED 0x0000018a 819 820/* Pentium IV performance counter MSRs */ 821#define MSR_P4_BPU_PERFCTR0 0x00000300 822#define MSR_P4_BPU_PERFCTR1 0x00000301 823#define MSR_P4_BPU_PERFCTR2 0x00000302 824#define MSR_P4_BPU_PERFCTR3 0x00000303 825#define MSR_P4_MS_PERFCTR0 0x00000304 826#define MSR_P4_MS_PERFCTR1 0x00000305 827#define MSR_P4_MS_PERFCTR2 0x00000306 828#define MSR_P4_MS_PERFCTR3 0x00000307 829#define MSR_P4_FLAME_PERFCTR0 0x00000308 830#define MSR_P4_FLAME_PERFCTR1 0x00000309 831#define MSR_P4_FLAME_PERFCTR2 0x0000030a 832#define MSR_P4_FLAME_PERFCTR3 0x0000030b 833#define MSR_P4_IQ_PERFCTR0 0x0000030c 834#define MSR_P4_IQ_PERFCTR1 0x0000030d 835#define MSR_P4_IQ_PERFCTR2 0x0000030e 836#define MSR_P4_IQ_PERFCTR3 0x0000030f 837#define MSR_P4_IQ_PERFCTR4 0x00000310 838#define MSR_P4_IQ_PERFCTR5 0x00000311 839#define MSR_P4_BPU_CCCR0 0x00000360 840#define MSR_P4_BPU_CCCR1 0x00000361 841#define MSR_P4_BPU_CCCR2 0x00000362 842#define MSR_P4_BPU_CCCR3 0x00000363 843#define MSR_P4_MS_CCCR0 0x00000364 844#define MSR_P4_MS_CCCR1 0x00000365 845#define MSR_P4_MS_CCCR2 0x00000366 846#define MSR_P4_MS_CCCR3 0x00000367 847#define MSR_P4_FLAME_CCCR0 0x00000368 848#define MSR_P4_FLAME_CCCR1 0x00000369 849#define MSR_P4_FLAME_CCCR2 0x0000036a 850#define MSR_P4_FLAME_CCCR3 0x0000036b 851#define MSR_P4_IQ_CCCR0 0x0000036c 852#define MSR_P4_IQ_CCCR1 0x0000036d 853#define MSR_P4_IQ_CCCR2 0x0000036e 854#define MSR_P4_IQ_CCCR3 0x0000036f 855#define MSR_P4_IQ_CCCR4 0x00000370 856#define MSR_P4_IQ_CCCR5 0x00000371 857#define MSR_P4_ALF_ESCR0 0x000003ca 858#define MSR_P4_ALF_ESCR1 0x000003cb 859#define MSR_P4_BPU_ESCR0 0x000003b2 860#define MSR_P4_BPU_ESCR1 0x000003b3 861#define MSR_P4_BSU_ESCR0 0x000003a0 862#define MSR_P4_BSU_ESCR1 0x000003a1 863#define MSR_P4_CRU_ESCR0 0x000003b8 864#define MSR_P4_CRU_ESCR1 0x000003b9 865#define MSR_P4_CRU_ESCR2 0x000003cc 866#define MSR_P4_CRU_ESCR3 0x000003cd 867#define MSR_P4_CRU_ESCR4 0x000003e0 868#define MSR_P4_CRU_ESCR5 0x000003e1 869#define MSR_P4_DAC_ESCR0 0x000003a8 870#define MSR_P4_DAC_ESCR1 0x000003a9 871#define MSR_P4_FIRM_ESCR0 0x000003a4 872#define MSR_P4_FIRM_ESCR1 0x000003a5 873#define MSR_P4_FLAME_ESCR0 0x000003a6 874#define MSR_P4_FLAME_ESCR1 0x000003a7 875#define MSR_P4_FSB_ESCR0 0x000003a2 876#define MSR_P4_FSB_ESCR1 0x000003a3 877#define MSR_P4_IQ_ESCR0 0x000003ba 878#define MSR_P4_IQ_ESCR1 0x000003bb 879#define MSR_P4_IS_ESCR0 0x000003b4 880#define MSR_P4_IS_ESCR1 0x000003b5 881#define MSR_P4_ITLB_ESCR0 0x000003b6 882#define MSR_P4_ITLB_ESCR1 0x000003b7 883#define MSR_P4_IX_ESCR0 0x000003c8 884#define MSR_P4_IX_ESCR1 0x000003c9 885#define MSR_P4_MOB_ESCR0 0x000003aa 886#define MSR_P4_MOB_ESCR1 0x000003ab 887#define MSR_P4_MS_ESCR0 0x000003c0 888#define MSR_P4_MS_ESCR1 0x000003c1 889#define MSR_P4_PMH_ESCR0 0x000003ac 890#define MSR_P4_PMH_ESCR1 0x000003ad 891#define MSR_P4_RAT_ESCR0 0x000003bc 892#define MSR_P4_RAT_ESCR1 0x000003bd 893#define MSR_P4_SAAT_ESCR0 0x000003ae 894#define MSR_P4_SAAT_ESCR1 0x000003af 895#define MSR_P4_SSU_ESCR0 0x000003be 896#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 897 898#define MSR_P4_TBPU_ESCR0 0x000003c2 899#define MSR_P4_TBPU_ESCR1 0x000003c3 900#define MSR_P4_TC_ESCR0 0x000003c4 901#define MSR_P4_TC_ESCR1 0x000003c5 902#define MSR_P4_U2L_ESCR0 0x000003b0 903#define MSR_P4_U2L_ESCR1 0x000003b1 904 905#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 906 907/* Intel Core-based CPU performance counters */ 908#define MSR_CORE_PERF_FIXED_CTR0 0x00000309 909#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 910#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 911#define MSR_CORE_PERF_FIXED_CTR3 0x0000030c 912#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 913#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 914#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 915#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 916 917#define MSR_PERF_METRICS 0x00000329 918 919/* PERF_GLOBAL_OVF_CTL bits */ 920#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 921#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 922#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 923#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 924#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 925#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 926 927/* Geode defined MSRs */ 928#define MSR_GEODE_BUSCONT_CONF0 0x00001900 929 930/* Intel VT MSRs */ 931#define MSR_IA32_VMX_BASIC 0x00000480 932#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 933#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 934#define MSR_IA32_VMX_EXIT_CTLS 0x00000483 935#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 936#define MSR_IA32_VMX_MISC 0x00000485 937#define MSR_IA32_VMX_CR0_FIXED0 0x00000486 938#define MSR_IA32_VMX_CR0_FIXED1 0x00000487 939#define MSR_IA32_VMX_CR4_FIXED0 0x00000488 940#define MSR_IA32_VMX_CR4_FIXED1 0x00000489 941#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 942#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 943#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 944#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 945#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 946#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 947#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 948#define MSR_IA32_VMX_VMFUNC 0x00000491 949 950/* VMX_BASIC bits and bitmasks */ 951#define VMX_BASIC_VMCS_SIZE_SHIFT 32 952#define VMX_BASIC_TRUE_CTLS (1ULL << 55) 953#define VMX_BASIC_64 0x0001000000000000LLU 954#define VMX_BASIC_MEM_TYPE_SHIFT 50 955#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 956#define VMX_BASIC_MEM_TYPE_WB 6LLU 957#define VMX_BASIC_INOUT 0x0040000000000000LLU 958 959/* MSR_IA32_VMX_MISC bits */ 960#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 961#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 962#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 963/* AMD-V MSRs */ 964 965#define MSR_VM_CR 0xc0010114 966#define MSR_VM_IGNNE 0xc0010115 967#define MSR_VM_HSAVE_PA 0xc0010117 968 969#endif /* _ASM_X86_MSR_INDEX_H */ 970