18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci#ifndef _TOOLS_LINUX_ASM_X86_BARRIER_H 38c2ecf20Sopenharmony_ci#define _TOOLS_LINUX_ASM_X86_BARRIER_H 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ci/* 68c2ecf20Sopenharmony_ci * Copied from the Linux kernel sources, and also moving code 78c2ecf20Sopenharmony_ci * out from tools/perf/perf-sys.h so as to make it be located 88c2ecf20Sopenharmony_ci * in a place similar as in the kernel sources. 98c2ecf20Sopenharmony_ci * 108c2ecf20Sopenharmony_ci * Force strict CPU ordering. 118c2ecf20Sopenharmony_ci * And yes, this is required on UP too when we're talking 128c2ecf20Sopenharmony_ci * to devices. 138c2ecf20Sopenharmony_ci */ 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci#if defined(__i386__) 168c2ecf20Sopenharmony_ci/* 178c2ecf20Sopenharmony_ci * Some non-Intel clones support out of order store. wmb() ceases to be a 188c2ecf20Sopenharmony_ci * nop for these. 198c2ecf20Sopenharmony_ci */ 208c2ecf20Sopenharmony_ci#define mb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory") 218c2ecf20Sopenharmony_ci#define rmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory") 228c2ecf20Sopenharmony_ci#define wmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory") 238c2ecf20Sopenharmony_ci#elif defined(__x86_64__) 248c2ecf20Sopenharmony_ci#define mb() asm volatile("mfence" ::: "memory") 258c2ecf20Sopenharmony_ci#define rmb() asm volatile("lfence" ::: "memory") 268c2ecf20Sopenharmony_ci#define wmb() asm volatile("sfence" ::: "memory") 278c2ecf20Sopenharmony_ci#define smp_rmb() barrier() 288c2ecf20Sopenharmony_ci#define smp_wmb() barrier() 298c2ecf20Sopenharmony_ci#define smp_mb() asm volatile("lock; addl $0,-132(%%rsp)" ::: "memory", "cc") 308c2ecf20Sopenharmony_ci#endif 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ci#if defined(__x86_64__) 338c2ecf20Sopenharmony_ci#define smp_store_release(p, v) \ 348c2ecf20Sopenharmony_cido { \ 358c2ecf20Sopenharmony_ci barrier(); \ 368c2ecf20Sopenharmony_ci WRITE_ONCE(*p, v); \ 378c2ecf20Sopenharmony_ci} while (0) 388c2ecf20Sopenharmony_ci 398c2ecf20Sopenharmony_ci#define smp_load_acquire(p) \ 408c2ecf20Sopenharmony_ci({ \ 418c2ecf20Sopenharmony_ci typeof(*p) ___p1 = READ_ONCE(*p); \ 428c2ecf20Sopenharmony_ci barrier(); \ 438c2ecf20Sopenharmony_ci ___p1; \ 448c2ecf20Sopenharmony_ci}) 458c2ecf20Sopenharmony_ci#endif /* defined(__x86_64__) */ 468c2ecf20Sopenharmony_ci#endif /* _TOOLS_LINUX_ASM_X86_BARRIER_H */ 47