18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copied from the kernel sources: 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima 68c2ecf20Sopenharmony_ci * Copyright (C) 2002 Paul Mundt 78c2ecf20Sopenharmony_ci */ 88c2ecf20Sopenharmony_ci#ifndef __TOOLS_LINUX_ASM_SH_BARRIER_H 98c2ecf20Sopenharmony_ci#define __TOOLS_LINUX_ASM_SH_BARRIER_H 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci/* 128c2ecf20Sopenharmony_ci * A brief note on ctrl_barrier(), the control register write barrier. 138c2ecf20Sopenharmony_ci * 148c2ecf20Sopenharmony_ci * Legacy SH cores typically require a sequence of 8 nops after 158c2ecf20Sopenharmony_ci * modification of a control register in order for the changes to take 168c2ecf20Sopenharmony_ci * effect. On newer cores (like the sh4a and sh5) this is accomplished 178c2ecf20Sopenharmony_ci * with icbi. 188c2ecf20Sopenharmony_ci * 198c2ecf20Sopenharmony_ci * Also note that on sh4a in the icbi case we can forego a synco for the 208c2ecf20Sopenharmony_ci * write barrier, as it's not necessary for control registers. 218c2ecf20Sopenharmony_ci * 228c2ecf20Sopenharmony_ci * Historically we have only done this type of barrier for the MMUCR, but 238c2ecf20Sopenharmony_ci * it's also necessary for the CCR, so we make it generic here instead. 248c2ecf20Sopenharmony_ci */ 258c2ecf20Sopenharmony_ci#if defined(__SH4A__) 268c2ecf20Sopenharmony_ci#define mb() __asm__ __volatile__ ("synco": : :"memory") 278c2ecf20Sopenharmony_ci#define rmb() mb() 288c2ecf20Sopenharmony_ci#define wmb() mb() 298c2ecf20Sopenharmony_ci#endif 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci#include <asm-generic/barrier.h> 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci#endif /* __TOOLS_LINUX_ASM_SH_BARRIER_H */ 34