18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (C) ST-Ericsson SA 2012 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Author: Ola Lilja <ola.o.lilja@stericsson.com>, 68c2ecf20Sopenharmony_ci * Roger Nilsson <roger.xr.nilsson@stericsson.com> 78c2ecf20Sopenharmony_ci * for ST-Ericsson. 88c2ecf20Sopenharmony_ci * 98c2ecf20Sopenharmony_ci * License terms: 108c2ecf20Sopenharmony_ci */ 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci#ifndef UX500_msp_dai_H 138c2ecf20Sopenharmony_ci#define UX500_msp_dai_H 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci#include <linux/types.h> 168c2ecf20Sopenharmony_ci#include <linux/spinlock.h> 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci#include "ux500_msp_i2s.h" 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ci#define UX500_NBR_OF_DAI 4 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci#define UX500_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | \ 238c2ecf20Sopenharmony_ci SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci#define UX500_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE) 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci#define FRAME_PER_SINGLE_SLOT_8_KHZ 31 288c2ecf20Sopenharmony_ci#define FRAME_PER_SINGLE_SLOT_16_KHZ 124 298c2ecf20Sopenharmony_ci#define FRAME_PER_SINGLE_SLOT_44_1_KHZ 63 308c2ecf20Sopenharmony_ci#define FRAME_PER_SINGLE_SLOT_48_KHZ 49 318c2ecf20Sopenharmony_ci#define FRAME_PER_2_SLOTS 31 328c2ecf20Sopenharmony_ci#define FRAME_PER_8_SLOTS 138 338c2ecf20Sopenharmony_ci#define FRAME_PER_16_SLOTS 277 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ci#define UX500_MSP_INTERNAL_CLOCK_FREQ 40000000 368c2ecf20Sopenharmony_ci#define UX500_MSP1_INTERNAL_CLOCK_FREQ UX500_MSP_INTERNAL_CLOCK_FREQ 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci#define UX500_MSP_MIN_CHANNELS 1 398c2ecf20Sopenharmony_ci#define UX500_MSP_MAX_CHANNELS 8 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci#define PLAYBACK_CONFIGURED 1 428c2ecf20Sopenharmony_ci#define CAPTURE_CONFIGURED 2 438c2ecf20Sopenharmony_ci 448c2ecf20Sopenharmony_cienum ux500_msp_clock_id { 458c2ecf20Sopenharmony_ci UX500_MSP_MASTER_CLOCK, 468c2ecf20Sopenharmony_ci}; 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_cistruct ux500_msp_i2s_drvdata { 498c2ecf20Sopenharmony_ci struct ux500_msp *msp; 508c2ecf20Sopenharmony_ci struct regulator *reg_vape; 518c2ecf20Sopenharmony_ci unsigned int fmt; 528c2ecf20Sopenharmony_ci unsigned int tx_mask; 538c2ecf20Sopenharmony_ci unsigned int rx_mask; 548c2ecf20Sopenharmony_ci int slots; 558c2ecf20Sopenharmony_ci int slot_width; 568c2ecf20Sopenharmony_ci 578c2ecf20Sopenharmony_ci /* Clocks */ 588c2ecf20Sopenharmony_ci unsigned int master_clk; 598c2ecf20Sopenharmony_ci struct clk *clk; 608c2ecf20Sopenharmony_ci struct clk *pclk; 618c2ecf20Sopenharmony_ci 628c2ecf20Sopenharmony_ci /* Regulators */ 638c2ecf20Sopenharmony_ci int vape_opp_constraint; 648c2ecf20Sopenharmony_ci}; 658c2ecf20Sopenharmony_ci 668c2ecf20Sopenharmony_ciint ux500_msp_dai_set_data_delay(struct snd_soc_dai *dai, int delay); 678c2ecf20Sopenharmony_ci 688c2ecf20Sopenharmony_ci#endif 69