1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (C) 2015 Andrea Venturi 4 * Andrea Venturi <be17068@iperbole.bo.it> 5 * 6 * Copyright (C) 2016 Maxime Ripard 7 * Maxime Ripard <maxime.ripard@free-electrons.com> 8 */ 9 10#include <linux/clk.h> 11#include <linux/dmaengine.h> 12#include <linux/module.h> 13#include <linux/of_device.h> 14#include <linux/platform_device.h> 15#include <linux/pm_runtime.h> 16#include <linux/regmap.h> 17#include <linux/reset.h> 18 19#include <sound/dmaengine_pcm.h> 20#include <sound/pcm_params.h> 21#include <sound/soc.h> 22#include <sound/soc-dai.h> 23 24#define SUN4I_I2S_CTRL_REG 0x00 25#define SUN4I_I2S_CTRL_SDO_EN_MASK GENMASK(11, 8) 26#define SUN4I_I2S_CTRL_SDO_EN(sdo) BIT(8 + (sdo)) 27#define SUN4I_I2S_CTRL_MODE_MASK BIT(5) 28#define SUN4I_I2S_CTRL_MODE_SLAVE (1 << 5) 29#define SUN4I_I2S_CTRL_MODE_MASTER (0 << 5) 30#define SUN4I_I2S_CTRL_TX_EN BIT(2) 31#define SUN4I_I2S_CTRL_RX_EN BIT(1) 32#define SUN4I_I2S_CTRL_GL_EN BIT(0) 33 34#define SUN4I_I2S_FMT0_REG 0x04 35#define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(7) 36#define SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 7) 37#define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 7) 38#define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK BIT(6) 39#define SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 6) 40#define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 6) 41#define SUN4I_I2S_FMT0_SR_MASK GENMASK(5, 4) 42#define SUN4I_I2S_FMT0_SR(sr) ((sr) << 4) 43#define SUN4I_I2S_FMT0_WSS_MASK GENMASK(3, 2) 44#define SUN4I_I2S_FMT0_WSS(wss) ((wss) << 2) 45#define SUN4I_I2S_FMT0_FMT_MASK GENMASK(1, 0) 46#define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0) 47#define SUN4I_I2S_FMT0_FMT_LEFT_J (1 << 0) 48#define SUN4I_I2S_FMT0_FMT_I2S (0 << 0) 49 50#define SUN4I_I2S_FMT1_REG 0x08 51#define SUN4I_I2S_FIFO_TX_REG 0x0c 52#define SUN4I_I2S_FIFO_RX_REG 0x10 53 54#define SUN4I_I2S_FIFO_CTRL_REG 0x14 55#define SUN4I_I2S_FIFO_CTRL_FLUSH_TX BIT(25) 56#define SUN4I_I2S_FIFO_CTRL_FLUSH_RX BIT(24) 57#define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK BIT(2) 58#define SUN4I_I2S_FIFO_CTRL_TX_MODE(mode) ((mode) << 2) 59#define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK GENMASK(1, 0) 60#define SUN4I_I2S_FIFO_CTRL_RX_MODE(mode) (mode) 61 62#define SUN4I_I2S_FIFO_STA_REG 0x18 63 64#define SUN4I_I2S_DMA_INT_CTRL_REG 0x1c 65#define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN BIT(7) 66#define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN BIT(3) 67 68#define SUN4I_I2S_INT_STA_REG 0x20 69 70#define SUN4I_I2S_CLK_DIV_REG 0x24 71#define SUN4I_I2S_CLK_DIV_MCLK_EN BIT(7) 72#define SUN4I_I2S_CLK_DIV_BCLK_MASK GENMASK(6, 4) 73#define SUN4I_I2S_CLK_DIV_BCLK(bclk) ((bclk) << 4) 74#define SUN4I_I2S_CLK_DIV_MCLK_MASK GENMASK(3, 0) 75#define SUN4I_I2S_CLK_DIV_MCLK(mclk) ((mclk) << 0) 76 77#define SUN4I_I2S_TX_CNT_REG 0x28 78#define SUN4I_I2S_RX_CNT_REG 0x2c 79 80#define SUN4I_I2S_TX_CHAN_SEL_REG 0x30 81#define SUN4I_I2S_CHAN_SEL_MASK GENMASK(2, 0) 82#define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0) 83 84#define SUN4I_I2S_TX_CHAN_MAP_REG 0x34 85#define SUN4I_I2S_TX_CHAN_MAP(chan, sample) ((sample) << (chan << 2)) 86 87#define SUN4I_I2S_RX_CHAN_SEL_REG 0x38 88#define SUN4I_I2S_RX_CHAN_MAP_REG 0x3c 89 90/* Defines required for sun8i-h3 support */ 91#define SUN8I_I2S_CTRL_BCLK_OUT BIT(18) 92#define SUN8I_I2S_CTRL_LRCK_OUT BIT(17) 93 94#define SUN8I_I2S_CTRL_MODE_MASK GENMASK(5, 4) 95#define SUN8I_I2S_CTRL_MODE_RIGHT (2 << 4) 96#define SUN8I_I2S_CTRL_MODE_LEFT (1 << 4) 97#define SUN8I_I2S_CTRL_MODE_PCM (0 << 4) 98 99#define SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(19) 100#define SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 19) 101#define SUN8I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 19) 102#define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8) 103#define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8) 104#define SUN8I_I2S_FMT0_BCLK_POLARITY_MASK BIT(7) 105#define SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 7) 106#define SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 7) 107 108#define SUN8I_I2S_INT_STA_REG 0x0c 109#define SUN8I_I2S_FIFO_TX_REG 0x20 110 111#define SUN8I_I2S_CHAN_CFG_REG 0x30 112#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK GENMASK(6, 4) 113#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4) 114#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK GENMASK(2, 0) 115#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1) 116 117#define SUN8I_I2S_TX_CHAN_MAP_REG 0x44 118#define SUN8I_I2S_TX_CHAN_SEL_REG 0x34 119#define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13, 12) 120#define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 12) 121#define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4) 122#define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4) 123 124#define SUN8I_I2S_RX_CHAN_SEL_REG 0x54 125#define SUN8I_I2S_RX_CHAN_MAP_REG 0x58 126 127struct sun4i_i2s; 128 129/** 130 * struct sun4i_i2s_quirks - Differences between SoC variants. 131 * @has_reset: SoC needs reset deasserted. 132 * @reg_offset_txdata: offset of the tx fifo. 133 * @sun4i_i2s_regmap: regmap config to use. 134 * @field_clkdiv_mclk_en: regmap field to enable mclk output. 135 * @field_fmt_wss: regmap field to set word select size. 136 * @field_fmt_sr: regmap field to set sample resolution. 137 * @bclk_dividers: bit clock dividers array 138 * @num_bclk_dividers: number of bit clock dividers 139 * @mclk_dividers: mclk dividers array 140 * @num_mclk_dividers: number of mclk dividers 141 * @get_bclk_parent_rate: callback to get bclk parent rate 142 * @get_sr: callback to get sample resolution 143 * @get_wss: callback to get word select size 144 * @set_chan_cfg: callback to set channel configuration 145 * @set_fmt: callback to set format 146 */ 147struct sun4i_i2s_quirks { 148 bool has_reset; 149 unsigned int reg_offset_txdata; /* TX FIFO */ 150 const struct regmap_config *sun4i_i2s_regmap; 151 152 /* Register fields for i2s */ 153 struct reg_field field_clkdiv_mclk_en; 154 struct reg_field field_fmt_wss; 155 struct reg_field field_fmt_sr; 156 157 const struct sun4i_i2s_clk_div *bclk_dividers; 158 unsigned int num_bclk_dividers; 159 const struct sun4i_i2s_clk_div *mclk_dividers; 160 unsigned int num_mclk_dividers; 161 162 unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *); 163 s8 (*get_sr)(const struct sun4i_i2s *, int); 164 s8 (*get_wss)(const struct sun4i_i2s *, int); 165 int (*set_chan_cfg)(const struct sun4i_i2s *, 166 const struct snd_pcm_hw_params *); 167 int (*set_fmt)(const struct sun4i_i2s *, unsigned int); 168}; 169 170struct sun4i_i2s { 171 struct clk *bus_clk; 172 struct clk *mod_clk; 173 struct regmap *regmap; 174 struct reset_control *rst; 175 176 unsigned int format; 177 unsigned int mclk_freq; 178 unsigned int slots; 179 unsigned int slot_width; 180 181 struct snd_dmaengine_dai_dma_data capture_dma_data; 182 struct snd_dmaengine_dai_dma_data playback_dma_data; 183 184 /* Register fields for i2s */ 185 struct regmap_field *field_clkdiv_mclk_en; 186 struct regmap_field *field_fmt_wss; 187 struct regmap_field *field_fmt_sr; 188 189 const struct sun4i_i2s_quirks *variant; 190}; 191 192struct sun4i_i2s_clk_div { 193 u8 div; 194 u8 val; 195}; 196 197static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] = { 198 { .div = 2, .val = 0 }, 199 { .div = 4, .val = 1 }, 200 { .div = 6, .val = 2 }, 201 { .div = 8, .val = 3 }, 202 { .div = 12, .val = 4 }, 203 { .div = 16, .val = 5 }, 204 /* TODO - extend divide ratio supported by newer SoCs */ 205}; 206 207static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = { 208 { .div = 1, .val = 0 }, 209 { .div = 2, .val = 1 }, 210 { .div = 4, .val = 2 }, 211 { .div = 6, .val = 3 }, 212 { .div = 8, .val = 4 }, 213 { .div = 12, .val = 5 }, 214 { .div = 16, .val = 6 }, 215 { .div = 24, .val = 7 }, 216 /* TODO - extend divide ratio supported by newer SoCs */ 217}; 218 219static const struct sun4i_i2s_clk_div sun8i_i2s_clk_div[] = { 220 { .div = 1, .val = 1 }, 221 { .div = 2, .val = 2 }, 222 { .div = 4, .val = 3 }, 223 { .div = 6, .val = 4 }, 224 { .div = 8, .val = 5 }, 225 { .div = 12, .val = 6 }, 226 { .div = 16, .val = 7 }, 227 { .div = 24, .val = 8 }, 228 { .div = 32, .val = 9 }, 229 { .div = 48, .val = 10 }, 230 { .div = 64, .val = 11 }, 231 { .div = 96, .val = 12 }, 232 { .div = 128, .val = 13 }, 233 { .div = 176, .val = 14 }, 234 { .div = 192, .val = 15 }, 235}; 236 237static unsigned long sun4i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s) 238{ 239 return i2s->mclk_freq; 240} 241 242static unsigned long sun8i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s) 243{ 244 return clk_get_rate(i2s->mod_clk); 245} 246 247static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s, 248 unsigned long parent_rate, 249 unsigned int sampling_rate, 250 unsigned int channels, 251 unsigned int word_size) 252{ 253 const struct sun4i_i2s_clk_div *dividers = i2s->variant->bclk_dividers; 254 int div = parent_rate / sampling_rate / word_size / channels; 255 int i; 256 257 for (i = 0; i < i2s->variant->num_bclk_dividers; i++) { 258 const struct sun4i_i2s_clk_div *bdiv = ÷rs[i]; 259 260 if (bdiv->div == div) 261 return bdiv->val; 262 } 263 264 return -EINVAL; 265} 266 267static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s, 268 unsigned long parent_rate, 269 unsigned long mclk_rate) 270{ 271 const struct sun4i_i2s_clk_div *dividers = i2s->variant->mclk_dividers; 272 int div = parent_rate / mclk_rate; 273 int i; 274 275 for (i = 0; i < i2s->variant->num_mclk_dividers; i++) { 276 const struct sun4i_i2s_clk_div *mdiv = ÷rs[i]; 277 278 if (mdiv->div == div) 279 return mdiv->val; 280 } 281 282 return -EINVAL; 283} 284 285static int sun4i_i2s_oversample_rates[] = { 128, 192, 256, 384, 512, 768 }; 286static bool sun4i_i2s_oversample_is_valid(unsigned int oversample) 287{ 288 int i; 289 290 for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++) 291 if (sun4i_i2s_oversample_rates[i] == oversample) 292 return true; 293 294 return false; 295} 296 297static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, 298 unsigned int rate, 299 unsigned int slots, 300 unsigned int slot_width) 301{ 302 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 303 unsigned int oversample_rate, clk_rate, bclk_parent_rate; 304 int bclk_div, mclk_div; 305 int ret; 306 307 switch (rate) { 308 case 176400: 309 case 88200: 310 case 44100: 311 case 22050: 312 case 11025: 313 clk_rate = 22579200; 314 break; 315 316 case 192000: 317 case 128000: 318 case 96000: 319 case 64000: 320 case 48000: 321 case 32000: 322 case 24000: 323 case 16000: 324 case 12000: 325 case 8000: 326 clk_rate = 24576000; 327 break; 328 329 default: 330 dev_err(dai->dev, "Unsupported sample rate: %u\n", rate); 331 return -EINVAL; 332 } 333 334 ret = clk_set_rate(i2s->mod_clk, clk_rate); 335 if (ret) 336 return ret; 337 338 oversample_rate = i2s->mclk_freq / rate; 339 if (!sun4i_i2s_oversample_is_valid(oversample_rate)) { 340 dev_err(dai->dev, "Unsupported oversample rate: %d\n", 341 oversample_rate); 342 return -EINVAL; 343 } 344 345 bclk_parent_rate = i2s->variant->get_bclk_parent_rate(i2s); 346 bclk_div = sun4i_i2s_get_bclk_div(i2s, bclk_parent_rate, 347 rate, slots, slot_width); 348 if (bclk_div < 0) { 349 dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div); 350 return -EINVAL; 351 } 352 353 mclk_div = sun4i_i2s_get_mclk_div(i2s, clk_rate, i2s->mclk_freq); 354 if (mclk_div < 0) { 355 dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div); 356 return -EINVAL; 357 } 358 359 regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG, 360 SUN4I_I2S_CLK_DIV_BCLK(bclk_div) | 361 SUN4I_I2S_CLK_DIV_MCLK(mclk_div)); 362 363 regmap_field_write(i2s->field_clkdiv_mclk_en, 1); 364 365 return 0; 366} 367 368static s8 sun4i_i2s_get_sr(const struct sun4i_i2s *i2s, int width) 369{ 370 if (width < 16 || width > 24) 371 return -EINVAL; 372 373 if (width % 4) 374 return -EINVAL; 375 376 return (width - 16) / 4; 377} 378 379static s8 sun4i_i2s_get_wss(const struct sun4i_i2s *i2s, int width) 380{ 381 if (width < 16 || width > 32) 382 return -EINVAL; 383 384 if (width % 4) 385 return -EINVAL; 386 387 return (width - 16) / 4; 388} 389 390static s8 sun8i_i2s_get_sr_wss(const struct sun4i_i2s *i2s, int width) 391{ 392 if (width % 4) 393 return -EINVAL; 394 395 if (width < 8 || width > 32) 396 return -EINVAL; 397 398 return (width - 8) / 4 + 1; 399} 400 401static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, 402 const struct snd_pcm_hw_params *params) 403{ 404 unsigned int channels = params_channels(params); 405 406 /* Map the channels for playback and capture */ 407 regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210); 408 regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210); 409 410 /* Configure the channels */ 411 regmap_update_bits(i2s->regmap, SUN4I_I2S_TX_CHAN_SEL_REG, 412 SUN4I_I2S_CHAN_SEL_MASK, 413 SUN4I_I2S_CHAN_SEL(channels)); 414 regmap_update_bits(i2s->regmap, SUN4I_I2S_RX_CHAN_SEL_REG, 415 SUN4I_I2S_CHAN_SEL_MASK, 416 SUN4I_I2S_CHAN_SEL(channels)); 417 418 return 0; 419} 420 421static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s, 422 const struct snd_pcm_hw_params *params) 423{ 424 unsigned int channels = params_channels(params); 425 unsigned int slots = channels; 426 unsigned int lrck_period; 427 428 if (i2s->slots) 429 slots = i2s->slots; 430 431 /* Map the channels for playback and capture */ 432 regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210); 433 regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210); 434 435 /* Configure the channels */ 436 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, 437 SUN4I_I2S_CHAN_SEL_MASK, 438 SUN4I_I2S_CHAN_SEL(channels)); 439 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, 440 SUN4I_I2S_CHAN_SEL_MASK, 441 SUN4I_I2S_CHAN_SEL(channels)); 442 443 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, 444 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK, 445 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels)); 446 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, 447 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK, 448 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels)); 449 450 switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) { 451 case SND_SOC_DAIFMT_DSP_A: 452 case SND_SOC_DAIFMT_DSP_B: 453 lrck_period = params_physical_width(params) * slots; 454 break; 455 456 case SND_SOC_DAIFMT_LEFT_J: 457 case SND_SOC_DAIFMT_RIGHT_J: 458 case SND_SOC_DAIFMT_I2S: 459 lrck_period = params_physical_width(params); 460 break; 461 462 default: 463 return -EINVAL; 464 } 465 466 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, 467 SUN8I_I2S_FMT0_LRCK_PERIOD_MASK, 468 SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period)); 469 470 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, 471 SUN8I_I2S_TX_CHAN_EN_MASK, 472 SUN8I_I2S_TX_CHAN_EN(channels)); 473 474 return 0; 475} 476 477static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, 478 struct snd_pcm_hw_params *params, 479 struct snd_soc_dai *dai) 480{ 481 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 482 unsigned int word_size = params_width(params); 483 unsigned int slot_width = params_physical_width(params); 484 unsigned int channels = params_channels(params); 485 unsigned int slots = channels; 486 int ret, sr, wss; 487 u32 width; 488 489 if (i2s->slots) 490 slots = i2s->slots; 491 492 if (i2s->slot_width) 493 slot_width = i2s->slot_width; 494 495 ret = i2s->variant->set_chan_cfg(i2s, params); 496 if (ret < 0) { 497 dev_err(dai->dev, "Invalid channel configuration\n"); 498 return ret; 499 } 500 501 switch (params_physical_width(params)) { 502 case 16: 503 width = DMA_SLAVE_BUSWIDTH_2_BYTES; 504 break; 505 default: 506 dev_err(dai->dev, "Unsupported physical sample width: %d\n", 507 params_physical_width(params)); 508 return -EINVAL; 509 } 510 i2s->playback_dma_data.addr_width = width; 511 512 sr = i2s->variant->get_sr(i2s, word_size); 513 if (sr < 0) 514 return -EINVAL; 515 516 wss = i2s->variant->get_wss(i2s, slot_width); 517 if (wss < 0) 518 return -EINVAL; 519 520 regmap_field_write(i2s->field_fmt_wss, wss); 521 regmap_field_write(i2s->field_fmt_sr, sr); 522 523 return sun4i_i2s_set_clk_rate(dai, params_rate(params), 524 slots, slot_width); 525} 526 527static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, 528 unsigned int fmt) 529{ 530 u32 val; 531 532 /* DAI clock polarity */ 533 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 534 case SND_SOC_DAIFMT_IB_IF: 535 /* Invert both clocks */ 536 val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED | 537 SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED; 538 break; 539 case SND_SOC_DAIFMT_IB_NF: 540 /* Invert bit clock */ 541 val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED; 542 break; 543 case SND_SOC_DAIFMT_NB_IF: 544 /* Invert frame clock */ 545 val = SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED; 546 break; 547 case SND_SOC_DAIFMT_NB_NF: 548 val = 0; 549 break; 550 default: 551 return -EINVAL; 552 } 553 554 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, 555 SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK | 556 SUN4I_I2S_FMT0_BCLK_POLARITY_MASK, 557 val); 558 559 /* DAI Mode */ 560 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 561 case SND_SOC_DAIFMT_I2S: 562 val = SUN4I_I2S_FMT0_FMT_I2S; 563 break; 564 565 case SND_SOC_DAIFMT_LEFT_J: 566 val = SUN4I_I2S_FMT0_FMT_LEFT_J; 567 break; 568 569 case SND_SOC_DAIFMT_RIGHT_J: 570 val = SUN4I_I2S_FMT0_FMT_RIGHT_J; 571 break; 572 573 default: 574 return -EINVAL; 575 } 576 577 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, 578 SUN4I_I2S_FMT0_FMT_MASK, val); 579 580 /* DAI clock master masks */ 581 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 582 case SND_SOC_DAIFMT_CBS_CFS: 583 /* BCLK and LRCLK master */ 584 val = SUN4I_I2S_CTRL_MODE_MASTER; 585 break; 586 587 case SND_SOC_DAIFMT_CBM_CFM: 588 /* BCLK and LRCLK slave */ 589 val = SUN4I_I2S_CTRL_MODE_SLAVE; 590 break; 591 592 default: 593 return -EINVAL; 594 } 595 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 596 SUN4I_I2S_CTRL_MODE_MASK, val); 597 return 0; 598} 599 600static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, 601 unsigned int fmt) 602{ 603 u32 mode, val; 604 u8 offset; 605 606 /* 607 * DAI clock polarity 608 * 609 * The setup for LRCK contradicts the datasheet, but under a 610 * scope it's clear that the LRCK polarity is reversed 611 * compared to the expected polarity on the bus. 612 */ 613 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 614 case SND_SOC_DAIFMT_IB_IF: 615 /* Invert both clocks */ 616 val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED; 617 break; 618 case SND_SOC_DAIFMT_IB_NF: 619 /* Invert bit clock */ 620 val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED | 621 SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED; 622 break; 623 case SND_SOC_DAIFMT_NB_IF: 624 /* Invert frame clock */ 625 val = 0; 626 break; 627 case SND_SOC_DAIFMT_NB_NF: 628 val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED; 629 break; 630 default: 631 return -EINVAL; 632 } 633 634 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, 635 SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK | 636 SUN8I_I2S_FMT0_BCLK_POLARITY_MASK, 637 val); 638 639 /* DAI Mode */ 640 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 641 case SND_SOC_DAIFMT_DSP_A: 642 mode = SUN8I_I2S_CTRL_MODE_PCM; 643 offset = 1; 644 break; 645 646 case SND_SOC_DAIFMT_DSP_B: 647 mode = SUN8I_I2S_CTRL_MODE_PCM; 648 offset = 0; 649 break; 650 651 case SND_SOC_DAIFMT_I2S: 652 mode = SUN8I_I2S_CTRL_MODE_LEFT; 653 offset = 1; 654 break; 655 656 case SND_SOC_DAIFMT_LEFT_J: 657 mode = SUN8I_I2S_CTRL_MODE_LEFT; 658 offset = 0; 659 break; 660 661 case SND_SOC_DAIFMT_RIGHT_J: 662 mode = SUN8I_I2S_CTRL_MODE_RIGHT; 663 offset = 0; 664 break; 665 666 default: 667 return -EINVAL; 668 } 669 670 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 671 SUN8I_I2S_CTRL_MODE_MASK, mode); 672 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, 673 SUN8I_I2S_TX_CHAN_OFFSET_MASK, 674 SUN8I_I2S_TX_CHAN_OFFSET(offset)); 675 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, 676 SUN8I_I2S_TX_CHAN_OFFSET_MASK, 677 SUN8I_I2S_TX_CHAN_OFFSET(offset)); 678 679 /* DAI clock master masks */ 680 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 681 case SND_SOC_DAIFMT_CBS_CFS: 682 /* BCLK and LRCLK master */ 683 val = SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT; 684 break; 685 686 case SND_SOC_DAIFMT_CBM_CFM: 687 /* BCLK and LRCLK slave */ 688 val = 0; 689 break; 690 691 default: 692 return -EINVAL; 693 } 694 695 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 696 SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT, 697 val); 698 699 return 0; 700} 701 702static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 703{ 704 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 705 int ret; 706 707 ret = i2s->variant->set_fmt(i2s, fmt); 708 if (ret) { 709 dev_err(dai->dev, "Unsupported format configuration\n"); 710 return ret; 711 } 712 713 /* Set significant bits in our FIFOs */ 714 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, 715 SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK | 716 SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK, 717 SUN4I_I2S_FIFO_CTRL_TX_MODE(1) | 718 SUN4I_I2S_FIFO_CTRL_RX_MODE(1)); 719 720 i2s->format = fmt; 721 722 return 0; 723} 724 725static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s) 726{ 727 /* Flush RX FIFO */ 728 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, 729 SUN4I_I2S_FIFO_CTRL_FLUSH_RX, 730 SUN4I_I2S_FIFO_CTRL_FLUSH_RX); 731 732 /* Clear RX counter */ 733 regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0); 734 735 /* Enable RX Block */ 736 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 737 SUN4I_I2S_CTRL_RX_EN, 738 SUN4I_I2S_CTRL_RX_EN); 739 740 /* Enable RX DRQ */ 741 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 742 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN, 743 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN); 744} 745 746static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s) 747{ 748 /* Flush TX FIFO */ 749 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, 750 SUN4I_I2S_FIFO_CTRL_FLUSH_TX, 751 SUN4I_I2S_FIFO_CTRL_FLUSH_TX); 752 753 /* Clear TX counter */ 754 regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0); 755 756 /* Enable TX Block */ 757 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 758 SUN4I_I2S_CTRL_TX_EN, 759 SUN4I_I2S_CTRL_TX_EN); 760 761 /* Enable TX DRQ */ 762 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 763 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN, 764 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN); 765} 766 767static void sun4i_i2s_stop_capture(struct sun4i_i2s *i2s) 768{ 769 /* Disable RX Block */ 770 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 771 SUN4I_I2S_CTRL_RX_EN, 772 0); 773 774 /* Disable RX DRQ */ 775 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 776 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN, 777 0); 778} 779 780static void sun4i_i2s_stop_playback(struct sun4i_i2s *i2s) 781{ 782 /* Disable TX Block */ 783 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 784 SUN4I_I2S_CTRL_TX_EN, 785 0); 786 787 /* Disable TX DRQ */ 788 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, 789 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN, 790 0); 791} 792 793static int sun4i_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 794 struct snd_soc_dai *dai) 795{ 796 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 797 798 switch (cmd) { 799 case SNDRV_PCM_TRIGGER_START: 800 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 801 case SNDRV_PCM_TRIGGER_RESUME: 802 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 803 sun4i_i2s_start_playback(i2s); 804 else 805 sun4i_i2s_start_capture(i2s); 806 break; 807 808 case SNDRV_PCM_TRIGGER_STOP: 809 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 810 case SNDRV_PCM_TRIGGER_SUSPEND: 811 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 812 sun4i_i2s_stop_playback(i2s); 813 else 814 sun4i_i2s_stop_capture(i2s); 815 break; 816 817 default: 818 return -EINVAL; 819 } 820 821 return 0; 822} 823 824static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, 825 unsigned int freq, int dir) 826{ 827 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 828 829 if (clk_id != 0) 830 return -EINVAL; 831 832 i2s->mclk_freq = freq; 833 834 return 0; 835} 836 837static int sun4i_i2s_set_tdm_slot(struct snd_soc_dai *dai, 838 unsigned int tx_mask, unsigned int rx_mask, 839 int slots, int slot_width) 840{ 841 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 842 843 if (slots > 8) 844 return -EINVAL; 845 846 i2s->slots = slots; 847 i2s->slot_width = slot_width; 848 849 return 0; 850} 851 852static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = { 853 .hw_params = sun4i_i2s_hw_params, 854 .set_fmt = sun4i_i2s_set_fmt, 855 .set_sysclk = sun4i_i2s_set_sysclk, 856 .set_tdm_slot = sun4i_i2s_set_tdm_slot, 857 .trigger = sun4i_i2s_trigger, 858}; 859 860static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai) 861{ 862 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); 863 864 snd_soc_dai_init_dma_data(dai, 865 &i2s->playback_dma_data, 866 &i2s->capture_dma_data); 867 868 snd_soc_dai_set_drvdata(dai, i2s); 869 870 return 0; 871} 872 873static struct snd_soc_dai_driver sun4i_i2s_dai = { 874 .probe = sun4i_i2s_dai_probe, 875 .capture = { 876 .stream_name = "Capture", 877 .channels_min = 1, 878 .channels_max = 8, 879 .rates = SNDRV_PCM_RATE_8000_192000, 880 .formats = SNDRV_PCM_FMTBIT_S16_LE, 881 }, 882 .playback = { 883 .stream_name = "Playback", 884 .channels_min = 1, 885 .channels_max = 8, 886 .rates = SNDRV_PCM_RATE_8000_192000, 887 .formats = SNDRV_PCM_FMTBIT_S16_LE, 888 }, 889 .ops = &sun4i_i2s_dai_ops, 890 .symmetric_rates = 1, 891}; 892 893static const struct snd_soc_component_driver sun4i_i2s_component = { 894 .name = "sun4i-dai", 895}; 896 897static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg) 898{ 899 switch (reg) { 900 case SUN4I_I2S_FIFO_TX_REG: 901 return false; 902 903 default: 904 return true; 905 } 906} 907 908static bool sun4i_i2s_wr_reg(struct device *dev, unsigned int reg) 909{ 910 switch (reg) { 911 case SUN4I_I2S_FIFO_RX_REG: 912 case SUN4I_I2S_FIFO_STA_REG: 913 return false; 914 915 default: 916 return true; 917 } 918} 919 920static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg) 921{ 922 switch (reg) { 923 case SUN4I_I2S_FIFO_RX_REG: 924 case SUN4I_I2S_INT_STA_REG: 925 case SUN4I_I2S_RX_CNT_REG: 926 case SUN4I_I2S_TX_CNT_REG: 927 return true; 928 929 default: 930 return false; 931 } 932} 933 934static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg) 935{ 936 switch (reg) { 937 case SUN8I_I2S_FIFO_TX_REG: 938 return false; 939 940 default: 941 return true; 942 } 943} 944 945static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg) 946{ 947 if (reg == SUN8I_I2S_INT_STA_REG) 948 return true; 949 if (reg == SUN8I_I2S_FIFO_TX_REG) 950 return false; 951 952 return sun4i_i2s_volatile_reg(dev, reg); 953} 954 955static const struct reg_default sun4i_i2s_reg_defaults[] = { 956 { SUN4I_I2S_CTRL_REG, 0x00000000 }, 957 { SUN4I_I2S_FMT0_REG, 0x0000000c }, 958 { SUN4I_I2S_FMT1_REG, 0x00004020 }, 959 { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 }, 960 { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 }, 961 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 }, 962 { SUN4I_I2S_TX_CHAN_SEL_REG, 0x00000001 }, 963 { SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210 }, 964 { SUN4I_I2S_RX_CHAN_SEL_REG, 0x00000001 }, 965 { SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 }, 966}; 967 968static const struct reg_default sun8i_i2s_reg_defaults[] = { 969 { SUN4I_I2S_CTRL_REG, 0x00060000 }, 970 { SUN4I_I2S_FMT0_REG, 0x00000033 }, 971 { SUN4I_I2S_FMT1_REG, 0x00000030 }, 972 { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 }, 973 { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 }, 974 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 }, 975 { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 }, 976 { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 }, 977 { SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 }, 978 { SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 }, 979 { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 }, 980}; 981 982static const struct regmap_config sun4i_i2s_regmap_config = { 983 .reg_bits = 32, 984 .reg_stride = 4, 985 .val_bits = 32, 986 .max_register = SUN4I_I2S_RX_CHAN_MAP_REG, 987 988 .cache_type = REGCACHE_FLAT, 989 .reg_defaults = sun4i_i2s_reg_defaults, 990 .num_reg_defaults = ARRAY_SIZE(sun4i_i2s_reg_defaults), 991 .writeable_reg = sun4i_i2s_wr_reg, 992 .readable_reg = sun4i_i2s_rd_reg, 993 .volatile_reg = sun4i_i2s_volatile_reg, 994}; 995 996static const struct regmap_config sun8i_i2s_regmap_config = { 997 .reg_bits = 32, 998 .reg_stride = 4, 999 .val_bits = 32, 1000 .max_register = SUN8I_I2S_RX_CHAN_MAP_REG, 1001 .cache_type = REGCACHE_FLAT, 1002 .reg_defaults = sun8i_i2s_reg_defaults, 1003 .num_reg_defaults = ARRAY_SIZE(sun8i_i2s_reg_defaults), 1004 .writeable_reg = sun4i_i2s_wr_reg, 1005 .readable_reg = sun8i_i2s_rd_reg, 1006 .volatile_reg = sun8i_i2s_volatile_reg, 1007}; 1008 1009static int sun4i_i2s_runtime_resume(struct device *dev) 1010{ 1011 struct sun4i_i2s *i2s = dev_get_drvdata(dev); 1012 int ret; 1013 1014 ret = clk_prepare_enable(i2s->bus_clk); 1015 if (ret) { 1016 dev_err(dev, "Failed to enable bus clock\n"); 1017 return ret; 1018 } 1019 1020 regcache_cache_only(i2s->regmap, false); 1021 regcache_mark_dirty(i2s->regmap); 1022 1023 ret = regcache_sync(i2s->regmap); 1024 if (ret) { 1025 dev_err(dev, "Failed to sync regmap cache\n"); 1026 goto err_disable_clk; 1027 } 1028 1029 /* Enable the whole hardware block */ 1030 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 1031 SUN4I_I2S_CTRL_GL_EN, SUN4I_I2S_CTRL_GL_EN); 1032 1033 /* Enable the first output line */ 1034 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 1035 SUN4I_I2S_CTRL_SDO_EN_MASK, 1036 SUN4I_I2S_CTRL_SDO_EN(0)); 1037 1038 ret = clk_prepare_enable(i2s->mod_clk); 1039 if (ret) { 1040 dev_err(dev, "Failed to enable module clock\n"); 1041 goto err_disable_clk; 1042 } 1043 1044 return 0; 1045 1046err_disable_clk: 1047 clk_disable_unprepare(i2s->bus_clk); 1048 return ret; 1049} 1050 1051static int sun4i_i2s_runtime_suspend(struct device *dev) 1052{ 1053 struct sun4i_i2s *i2s = dev_get_drvdata(dev); 1054 1055 clk_disable_unprepare(i2s->mod_clk); 1056 1057 /* Disable our output lines */ 1058 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 1059 SUN4I_I2S_CTRL_SDO_EN_MASK, 0); 1060 1061 /* Disable the whole hardware block */ 1062 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, 1063 SUN4I_I2S_CTRL_GL_EN, 0); 1064 1065 regcache_cache_only(i2s->regmap, true); 1066 1067 clk_disable_unprepare(i2s->bus_clk); 1068 1069 return 0; 1070} 1071 1072static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { 1073 .has_reset = false, 1074 .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, 1075 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, 1076 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), 1077 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), 1078 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), 1079 .bclk_dividers = sun4i_i2s_bclk_div, 1080 .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div), 1081 .mclk_dividers = sun4i_i2s_mclk_div, 1082 .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div), 1083 .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate, 1084 .get_sr = sun4i_i2s_get_sr, 1085 .get_wss = sun4i_i2s_get_wss, 1086 .set_chan_cfg = sun4i_i2s_set_chan_cfg, 1087 .set_fmt = sun4i_i2s_set_soc_fmt, 1088}; 1089 1090static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { 1091 .has_reset = true, 1092 .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG, 1093 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, 1094 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), 1095 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), 1096 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), 1097 .bclk_dividers = sun4i_i2s_bclk_div, 1098 .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div), 1099 .mclk_dividers = sun4i_i2s_mclk_div, 1100 .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div), 1101 .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate, 1102 .get_sr = sun4i_i2s_get_sr, 1103 .get_wss = sun4i_i2s_get_wss, 1104 .set_chan_cfg = sun4i_i2s_set_chan_cfg, 1105 .set_fmt = sun4i_i2s_set_soc_fmt, 1106}; 1107 1108/* 1109 * This doesn't describe the TDM controller documented in the A83t 1110 * datasheet, but the three undocumented I2S controller that use the 1111 * older design. 1112 */ 1113static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = { 1114 .has_reset = true, 1115 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, 1116 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, 1117 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), 1118 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), 1119 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), 1120 .bclk_dividers = sun4i_i2s_bclk_div, 1121 .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div), 1122 .mclk_dividers = sun4i_i2s_mclk_div, 1123 .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div), 1124 .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate, 1125 .get_sr = sun4i_i2s_get_sr, 1126 .get_wss = sun4i_i2s_get_wss, 1127 .set_chan_cfg = sun4i_i2s_set_chan_cfg, 1128 .set_fmt = sun4i_i2s_set_soc_fmt, 1129}; 1130 1131static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { 1132 .has_reset = true, 1133 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, 1134 .sun4i_i2s_regmap = &sun8i_i2s_regmap_config, 1135 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), 1136 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), 1137 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6), 1138 .bclk_dividers = sun8i_i2s_clk_div, 1139 .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), 1140 .mclk_dividers = sun8i_i2s_clk_div, 1141 .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div), 1142 .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate, 1143 .get_sr = sun8i_i2s_get_sr_wss, 1144 .get_wss = sun8i_i2s_get_sr_wss, 1145 .set_chan_cfg = sun8i_i2s_set_chan_cfg, 1146 .set_fmt = sun8i_i2s_set_soc_fmt, 1147}; 1148 1149static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = { 1150 .has_reset = true, 1151 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, 1152 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config, 1153 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7), 1154 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3), 1155 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5), 1156 .bclk_dividers = sun4i_i2s_bclk_div, 1157 .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div), 1158 .mclk_dividers = sun4i_i2s_mclk_div, 1159 .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div), 1160 .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate, 1161 .get_sr = sun4i_i2s_get_sr, 1162 .get_wss = sun4i_i2s_get_wss, 1163 .set_chan_cfg = sun4i_i2s_set_chan_cfg, 1164 .set_fmt = sun4i_i2s_set_soc_fmt, 1165}; 1166 1167static int sun4i_i2s_init_regmap_fields(struct device *dev, 1168 struct sun4i_i2s *i2s) 1169{ 1170 i2s->field_clkdiv_mclk_en = 1171 devm_regmap_field_alloc(dev, i2s->regmap, 1172 i2s->variant->field_clkdiv_mclk_en); 1173 if (IS_ERR(i2s->field_clkdiv_mclk_en)) 1174 return PTR_ERR(i2s->field_clkdiv_mclk_en); 1175 1176 i2s->field_fmt_wss = 1177 devm_regmap_field_alloc(dev, i2s->regmap, 1178 i2s->variant->field_fmt_wss); 1179 if (IS_ERR(i2s->field_fmt_wss)) 1180 return PTR_ERR(i2s->field_fmt_wss); 1181 1182 i2s->field_fmt_sr = 1183 devm_regmap_field_alloc(dev, i2s->regmap, 1184 i2s->variant->field_fmt_sr); 1185 if (IS_ERR(i2s->field_fmt_sr)) 1186 return PTR_ERR(i2s->field_fmt_sr); 1187 1188 return 0; 1189} 1190 1191static int sun4i_i2s_probe(struct platform_device *pdev) 1192{ 1193 struct sun4i_i2s *i2s; 1194 struct resource *res; 1195 void __iomem *regs; 1196 int irq, ret; 1197 1198 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); 1199 if (!i2s) 1200 return -ENOMEM; 1201 platform_set_drvdata(pdev, i2s); 1202 1203 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1204 regs = devm_ioremap_resource(&pdev->dev, res); 1205 if (IS_ERR(regs)) 1206 return PTR_ERR(regs); 1207 1208 irq = platform_get_irq(pdev, 0); 1209 if (irq < 0) 1210 return irq; 1211 1212 i2s->variant = of_device_get_match_data(&pdev->dev); 1213 if (!i2s->variant) { 1214 dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); 1215 return -ENODEV; 1216 } 1217 1218 i2s->bus_clk = devm_clk_get(&pdev->dev, "apb"); 1219 if (IS_ERR(i2s->bus_clk)) { 1220 dev_err(&pdev->dev, "Can't get our bus clock\n"); 1221 return PTR_ERR(i2s->bus_clk); 1222 } 1223 1224 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 1225 i2s->variant->sun4i_i2s_regmap); 1226 if (IS_ERR(i2s->regmap)) { 1227 dev_err(&pdev->dev, "Regmap initialisation failed\n"); 1228 return PTR_ERR(i2s->regmap); 1229 } 1230 1231 i2s->mod_clk = devm_clk_get(&pdev->dev, "mod"); 1232 if (IS_ERR(i2s->mod_clk)) { 1233 dev_err(&pdev->dev, "Can't get our mod clock\n"); 1234 return PTR_ERR(i2s->mod_clk); 1235 } 1236 1237 if (i2s->variant->has_reset) { 1238 i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1239 if (IS_ERR(i2s->rst)) { 1240 dev_err(&pdev->dev, "Failed to get reset control\n"); 1241 return PTR_ERR(i2s->rst); 1242 } 1243 } 1244 1245 if (!IS_ERR(i2s->rst)) { 1246 ret = reset_control_deassert(i2s->rst); 1247 if (ret) { 1248 dev_err(&pdev->dev, 1249 "Failed to deassert the reset control\n"); 1250 return -EINVAL; 1251 } 1252 } 1253 1254 i2s->playback_dma_data.addr = res->start + 1255 i2s->variant->reg_offset_txdata; 1256 i2s->playback_dma_data.maxburst = 8; 1257 1258 i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG; 1259 i2s->capture_dma_data.maxburst = 8; 1260 1261 pm_runtime_enable(&pdev->dev); 1262 if (!pm_runtime_enabled(&pdev->dev)) { 1263 ret = sun4i_i2s_runtime_resume(&pdev->dev); 1264 if (ret) 1265 goto err_pm_disable; 1266 } 1267 1268 ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s); 1269 if (ret) { 1270 dev_err(&pdev->dev, "Could not initialise regmap fields\n"); 1271 goto err_suspend; 1272 } 1273 1274 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1275 if (ret) { 1276 dev_err(&pdev->dev, "Could not register PCM\n"); 1277 goto err_suspend; 1278 } 1279 1280 ret = devm_snd_soc_register_component(&pdev->dev, 1281 &sun4i_i2s_component, 1282 &sun4i_i2s_dai, 1); 1283 if (ret) { 1284 dev_err(&pdev->dev, "Could not register DAI\n"); 1285 goto err_suspend; 1286 } 1287 1288 return 0; 1289 1290err_suspend: 1291 if (!pm_runtime_status_suspended(&pdev->dev)) 1292 sun4i_i2s_runtime_suspend(&pdev->dev); 1293err_pm_disable: 1294 pm_runtime_disable(&pdev->dev); 1295 if (!IS_ERR(i2s->rst)) 1296 reset_control_assert(i2s->rst); 1297 1298 return ret; 1299} 1300 1301static int sun4i_i2s_remove(struct platform_device *pdev) 1302{ 1303 struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev); 1304 1305 pm_runtime_disable(&pdev->dev); 1306 if (!pm_runtime_status_suspended(&pdev->dev)) 1307 sun4i_i2s_runtime_suspend(&pdev->dev); 1308 1309 if (!IS_ERR(i2s->rst)) 1310 reset_control_assert(i2s->rst); 1311 1312 return 0; 1313} 1314 1315static const struct of_device_id sun4i_i2s_match[] = { 1316 { 1317 .compatible = "allwinner,sun4i-a10-i2s", 1318 .data = &sun4i_a10_i2s_quirks, 1319 }, 1320 { 1321 .compatible = "allwinner,sun6i-a31-i2s", 1322 .data = &sun6i_a31_i2s_quirks, 1323 }, 1324 { 1325 .compatible = "allwinner,sun8i-a83t-i2s", 1326 .data = &sun8i_a83t_i2s_quirks, 1327 }, 1328 { 1329 .compatible = "allwinner,sun8i-h3-i2s", 1330 .data = &sun8i_h3_i2s_quirks, 1331 }, 1332 { 1333 .compatible = "allwinner,sun50i-a64-codec-i2s", 1334 .data = &sun50i_a64_codec_i2s_quirks, 1335 }, 1336 {} 1337}; 1338MODULE_DEVICE_TABLE(of, sun4i_i2s_match); 1339 1340static const struct dev_pm_ops sun4i_i2s_pm_ops = { 1341 .runtime_resume = sun4i_i2s_runtime_resume, 1342 .runtime_suspend = sun4i_i2s_runtime_suspend, 1343}; 1344 1345static struct platform_driver sun4i_i2s_driver = { 1346 .probe = sun4i_i2s_probe, 1347 .remove = sun4i_i2s_remove, 1348 .driver = { 1349 .name = "sun4i-i2s", 1350 .of_match_table = sun4i_i2s_match, 1351 .pm = &sun4i_i2s_pm_ops, 1352 }, 1353}; 1354module_platform_driver(sun4i_i2s_driver); 1355 1356MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>"); 1357MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1358MODULE_DESCRIPTION("Allwinner A10 I2S driver"); 1359MODULE_LICENSE("GPL"); 1360