1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 7 */ 8 9#include <linux/clk.h> 10#include <linux/clk-provider.h> 11#include <linux/kernel.h> 12#include <linux/module.h> 13#include <linux/of_irq.h> 14#include <linux/of_platform.h> 15#include <linux/pm_runtime.h> 16#include <linux/regmap.h> 17 18#include <sound/asoundef.h> 19#include <sound/core.h> 20#include <sound/dmaengine_pcm.h> 21#include <sound/pcm_params.h> 22 23#include "stm32_sai.h" 24 25#define SAI_FREE_PROTOCOL 0x0 26#define SAI_SPDIF_PROTOCOL 0x1 27 28#define SAI_SLOT_SIZE_AUTO 0x0 29#define SAI_SLOT_SIZE_16 0x1 30#define SAI_SLOT_SIZE_32 0x2 31 32#define SAI_DATASIZE_8 0x2 33#define SAI_DATASIZE_10 0x3 34#define SAI_DATASIZE_16 0x4 35#define SAI_DATASIZE_20 0x5 36#define SAI_DATASIZE_24 0x6 37#define SAI_DATASIZE_32 0x7 38 39#define STM_SAI_DAI_NAME_SIZE 15 40 41#define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK) 42#define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE) 43 44#define STM_SAI_A_ID 0x0 45#define STM_SAI_B_ID 0x1 46 47#define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID) 48#define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID) 49#define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B") 50 51#define SAI_SYNC_NONE 0x0 52#define SAI_SYNC_INTERNAL 0x1 53#define SAI_SYNC_EXTERNAL 0x2 54 55#define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif) 56#define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm) 57#define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm) 58#define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata)) 59 60#define SAI_IEC60958_BLOCK_FRAMES 192 61#define SAI_IEC60958_STATUS_BYTES 24 62 63#define SAI_MCLK_NAME_LEN 32 64#define SAI_RATE_11K 11025 65 66/** 67 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B) 68 * @pdev: device data pointer 69 * @regmap: SAI register map pointer 70 * @regmap_config: SAI sub block register map configuration pointer 71 * @dma_params: dma configuration data for rx or tx channel 72 * @cpu_dai_drv: DAI driver data pointer 73 * @cpu_dai: DAI runtime data pointer 74 * @substream: PCM substream data pointer 75 * @pdata: SAI block parent data pointer 76 * @np_sync_provider: synchronization provider node 77 * @sai_ck: kernel clock feeding the SAI clock generator 78 * @sai_mclk: master clock from SAI mclk provider 79 * @phys_addr: SAI registers physical base address 80 * @mclk_rate: SAI block master clock frequency (Hz). set at init 81 * @id: SAI sub block id corresponding to sub-block A or B 82 * @dir: SAI block direction (playback or capture). set at init 83 * @master: SAI block mode flag. (true=master, false=slave) set at init 84 * @spdif: SAI S/PDIF iec60958 mode flag. set at init 85 * @fmt: SAI block format. relevant only for custom protocols. set at init 86 * @sync: SAI block synchronization mode. (none, internal or external) 87 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B) 88 * @synci: SAI block ext sync source (client setting). (SAI sync provider index) 89 * @fs_length: frame synchronization length. depends on protocol settings 90 * @slots: rx or tx slot number 91 * @slot_width: rx or tx slot width in bits 92 * @slot_mask: rx or tx active slots mask. set at init or at runtime 93 * @data_size: PCM data width. corresponds to PCM substream width. 94 * @spdif_frm_cnt: S/PDIF playback frame counter 95 * @iec958: iec958 data 96 * @ctrl_lock: control lock 97 * @irq_lock: prevent race condition with IRQ 98 */ 99struct stm32_sai_sub_data { 100 struct platform_device *pdev; 101 struct regmap *regmap; 102 const struct regmap_config *regmap_config; 103 struct snd_dmaengine_dai_dma_data dma_params; 104 struct snd_soc_dai_driver cpu_dai_drv; 105 struct snd_soc_dai *cpu_dai; 106 struct snd_pcm_substream *substream; 107 struct stm32_sai_data *pdata; 108 struct device_node *np_sync_provider; 109 struct clk *sai_ck; 110 struct clk *sai_mclk; 111 dma_addr_t phys_addr; 112 unsigned int mclk_rate; 113 unsigned int id; 114 int dir; 115 bool master; 116 bool spdif; 117 int fmt; 118 int sync; 119 int synco; 120 int synci; 121 int fs_length; 122 int slots; 123 int slot_width; 124 int slot_mask; 125 int data_size; 126 unsigned int spdif_frm_cnt; 127 struct snd_aes_iec958 iec958; 128 struct mutex ctrl_lock; /* protect resources accessed by controls */ 129 spinlock_t irq_lock; /* used to prevent race condition with IRQ */ 130}; 131 132enum stm32_sai_fifo_th { 133 STM_SAI_FIFO_TH_EMPTY, 134 STM_SAI_FIFO_TH_QUARTER, 135 STM_SAI_FIFO_TH_HALF, 136 STM_SAI_FIFO_TH_3_QUARTER, 137 STM_SAI_FIFO_TH_FULL, 138}; 139 140static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg) 141{ 142 switch (reg) { 143 case STM_SAI_CR1_REGX: 144 case STM_SAI_CR2_REGX: 145 case STM_SAI_FRCR_REGX: 146 case STM_SAI_SLOTR_REGX: 147 case STM_SAI_IMR_REGX: 148 case STM_SAI_SR_REGX: 149 case STM_SAI_CLRFR_REGX: 150 case STM_SAI_DR_REGX: 151 case STM_SAI_PDMCR_REGX: 152 case STM_SAI_PDMLY_REGX: 153 return true; 154 default: 155 return false; 156 } 157} 158 159static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg) 160{ 161 switch (reg) { 162 case STM_SAI_DR_REGX: 163 case STM_SAI_SR_REGX: 164 return true; 165 default: 166 return false; 167 } 168} 169 170static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg) 171{ 172 switch (reg) { 173 case STM_SAI_CR1_REGX: 174 case STM_SAI_CR2_REGX: 175 case STM_SAI_FRCR_REGX: 176 case STM_SAI_SLOTR_REGX: 177 case STM_SAI_IMR_REGX: 178 case STM_SAI_CLRFR_REGX: 179 case STM_SAI_DR_REGX: 180 case STM_SAI_PDMCR_REGX: 181 case STM_SAI_PDMLY_REGX: 182 return true; 183 default: 184 return false; 185 } 186} 187 188static int stm32_sai_sub_reg_up(struct stm32_sai_sub_data *sai, 189 unsigned int reg, unsigned int mask, 190 unsigned int val) 191{ 192 int ret; 193 194 ret = clk_enable(sai->pdata->pclk); 195 if (ret < 0) 196 return ret; 197 198 ret = regmap_update_bits(sai->regmap, reg, mask, val); 199 200 clk_disable(sai->pdata->pclk); 201 202 return ret; 203} 204 205static int stm32_sai_sub_reg_wr(struct stm32_sai_sub_data *sai, 206 unsigned int reg, unsigned int mask, 207 unsigned int val) 208{ 209 int ret; 210 211 ret = clk_enable(sai->pdata->pclk); 212 if (ret < 0) 213 return ret; 214 215 ret = regmap_write_bits(sai->regmap, reg, mask, val); 216 217 clk_disable(sai->pdata->pclk); 218 219 return ret; 220} 221 222static int stm32_sai_sub_reg_rd(struct stm32_sai_sub_data *sai, 223 unsigned int reg, unsigned int *val) 224{ 225 int ret; 226 227 ret = clk_enable(sai->pdata->pclk); 228 if (ret < 0) 229 return ret; 230 231 ret = regmap_read(sai->regmap, reg, val); 232 233 clk_disable(sai->pdata->pclk); 234 235 return ret; 236} 237 238static const struct regmap_config stm32_sai_sub_regmap_config_f4 = { 239 .reg_bits = 32, 240 .reg_stride = 4, 241 .val_bits = 32, 242 .max_register = STM_SAI_DR_REGX, 243 .readable_reg = stm32_sai_sub_readable_reg, 244 .volatile_reg = stm32_sai_sub_volatile_reg, 245 .writeable_reg = stm32_sai_sub_writeable_reg, 246 .fast_io = true, 247 .cache_type = REGCACHE_FLAT, 248}; 249 250static const struct regmap_config stm32_sai_sub_regmap_config_h7 = { 251 .reg_bits = 32, 252 .reg_stride = 4, 253 .val_bits = 32, 254 .max_register = STM_SAI_PDMLY_REGX, 255 .readable_reg = stm32_sai_sub_readable_reg, 256 .volatile_reg = stm32_sai_sub_volatile_reg, 257 .writeable_reg = stm32_sai_sub_writeable_reg, 258 .fast_io = true, 259 .cache_type = REGCACHE_FLAT, 260}; 261 262static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol, 263 struct snd_ctl_elem_info *uinfo) 264{ 265 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 266 uinfo->count = 1; 267 268 return 0; 269} 270 271static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol, 272 struct snd_ctl_elem_value *uctl) 273{ 274 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 275 276 mutex_lock(&sai->ctrl_lock); 277 memcpy(uctl->value.iec958.status, sai->iec958.status, 4); 278 mutex_unlock(&sai->ctrl_lock); 279 280 return 0; 281} 282 283static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol, 284 struct snd_ctl_elem_value *uctl) 285{ 286 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 287 288 mutex_lock(&sai->ctrl_lock); 289 memcpy(sai->iec958.status, uctl->value.iec958.status, 4); 290 mutex_unlock(&sai->ctrl_lock); 291 292 return 0; 293} 294 295static const struct snd_kcontrol_new iec958_ctls = { 296 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 297 SNDRV_CTL_ELEM_ACCESS_VOLATILE), 298 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 299 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 300 .info = snd_pcm_iec958_info, 301 .get = snd_pcm_iec958_get, 302 .put = snd_pcm_iec958_put, 303}; 304 305struct stm32_sai_mclk_data { 306 struct clk_hw hw; 307 unsigned long freq; 308 struct stm32_sai_sub_data *sai_data; 309}; 310 311#define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw) 312#define STM32_SAI_MAX_CLKS 1 313 314static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai, 315 unsigned long input_rate, 316 unsigned long output_rate) 317{ 318 int version = sai->pdata->conf.version; 319 int div; 320 321 div = DIV_ROUND_CLOSEST(input_rate, output_rate); 322 if (div > SAI_XCR1_MCKDIV_MAX(version)) { 323 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 324 return -EINVAL; 325 } 326 dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div); 327 328 if (input_rate % div) 329 dev_dbg(&sai->pdev->dev, 330 "Rate not accurate. requested (%ld), actual (%ld)\n", 331 output_rate, input_rate / div); 332 333 return div; 334} 335 336static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai, 337 unsigned int div) 338{ 339 int version = sai->pdata->conf.version; 340 int ret, cr1, mask; 341 342 if (div > SAI_XCR1_MCKDIV_MAX(version)) { 343 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 344 return -EINVAL; 345 } 346 347 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version)); 348 cr1 = SAI_XCR1_MCKDIV_SET(div); 349 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, mask, cr1); 350 if (ret < 0) 351 dev_err(&sai->pdev->dev, "Failed to update CR1 register\n"); 352 353 return ret; 354} 355 356static int stm32_sai_set_parent_clock(struct stm32_sai_sub_data *sai, 357 unsigned int rate) 358{ 359 struct platform_device *pdev = sai->pdev; 360 struct clk *parent_clk = sai->pdata->clk_x8k; 361 int ret; 362 363 if (!(rate % SAI_RATE_11K)) 364 parent_clk = sai->pdata->clk_x11k; 365 366 ret = clk_set_parent(sai->sai_ck, parent_clk); 367 if (ret) 368 dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s", 369 ret, ret == -EBUSY ? 370 "Active stream rates conflict\n" : "\n"); 371 372 return ret; 373} 374 375static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate, 376 unsigned long *prate) 377{ 378 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 379 struct stm32_sai_sub_data *sai = mclk->sai_data; 380 int div; 381 382 div = stm32_sai_get_clk_div(sai, *prate, rate); 383 if (div < 0) 384 return div; 385 386 mclk->freq = *prate / div; 387 388 return mclk->freq; 389} 390 391static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw, 392 unsigned long parent_rate) 393{ 394 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 395 396 return mclk->freq; 397} 398 399static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate, 400 unsigned long parent_rate) 401{ 402 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 403 struct stm32_sai_sub_data *sai = mclk->sai_data; 404 int div, ret; 405 406 div = stm32_sai_get_clk_div(sai, parent_rate, rate); 407 if (div < 0) 408 return div; 409 410 ret = stm32_sai_set_clk_div(sai, div); 411 if (ret) 412 return ret; 413 414 mclk->freq = rate; 415 416 return 0; 417} 418 419static int stm32_sai_mclk_enable(struct clk_hw *hw) 420{ 421 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 422 struct stm32_sai_sub_data *sai = mclk->sai_data; 423 424 dev_dbg(&sai->pdev->dev, "Enable master clock\n"); 425 426 return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 427 SAI_XCR1_MCKEN, SAI_XCR1_MCKEN); 428} 429 430static void stm32_sai_mclk_disable(struct clk_hw *hw) 431{ 432 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 433 struct stm32_sai_sub_data *sai = mclk->sai_data; 434 435 dev_dbg(&sai->pdev->dev, "Disable master clock\n"); 436 437 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0); 438} 439 440static const struct clk_ops mclk_ops = { 441 .enable = stm32_sai_mclk_enable, 442 .disable = stm32_sai_mclk_disable, 443 .recalc_rate = stm32_sai_mclk_recalc_rate, 444 .round_rate = stm32_sai_mclk_round_rate, 445 .set_rate = stm32_sai_mclk_set_rate, 446}; 447 448static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai) 449{ 450 struct clk_hw *hw; 451 struct stm32_sai_mclk_data *mclk; 452 struct device *dev = &sai->pdev->dev; 453 const char *pname = __clk_get_name(sai->sai_ck); 454 char *mclk_name, *p, *s = (char *)pname; 455 int ret, i = 0; 456 457 mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL); 458 if (!mclk) 459 return -ENOMEM; 460 461 mclk_name = devm_kcalloc(dev, sizeof(char), 462 SAI_MCLK_NAME_LEN, GFP_KERNEL); 463 if (!mclk_name) 464 return -ENOMEM; 465 466 /* 467 * Forge mclk clock name from parent clock name and suffix. 468 * String after "_" char is stripped in parent name. 469 */ 470 p = mclk_name; 471 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) { 472 *p++ = *s++; 473 i++; 474 } 475 STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk"); 476 477 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); 478 mclk->sai_data = sai; 479 hw = &mclk->hw; 480 481 dev_dbg(dev, "Register master clock %s\n", mclk_name); 482 ret = devm_clk_hw_register(&sai->pdev->dev, hw); 483 if (ret) { 484 dev_err(dev, "mclk register returned %d\n", ret); 485 return ret; 486 } 487 sai->sai_mclk = hw->clk; 488 489 /* register mclk provider */ 490 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 491} 492 493static irqreturn_t stm32_sai_isr(int irq, void *devid) 494{ 495 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid; 496 struct platform_device *pdev = sai->pdev; 497 unsigned int sr, imr, flags; 498 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING; 499 500 stm32_sai_sub_reg_rd(sai, STM_SAI_IMR_REGX, &imr); 501 stm32_sai_sub_reg_rd(sai, STM_SAI_SR_REGX, &sr); 502 503 flags = sr & imr; 504 if (!flags) 505 return IRQ_NONE; 506 507 stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK, 508 SAI_XCLRFR_MASK); 509 510 if (!sai->substream) { 511 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr); 512 return IRQ_NONE; 513 } 514 515 if (flags & SAI_XIMR_OVRUDRIE) { 516 dev_err(&pdev->dev, "IRQ %s\n", 517 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun"); 518 status = SNDRV_PCM_STATE_XRUN; 519 } 520 521 if (flags & SAI_XIMR_MUTEDETIE) 522 dev_dbg(&pdev->dev, "IRQ mute detected\n"); 523 524 if (flags & SAI_XIMR_WCKCFGIE) { 525 dev_err(&pdev->dev, "IRQ wrong clock configuration\n"); 526 status = SNDRV_PCM_STATE_DISCONNECTED; 527 } 528 529 if (flags & SAI_XIMR_CNRDYIE) 530 dev_err(&pdev->dev, "IRQ Codec not ready\n"); 531 532 if (flags & SAI_XIMR_AFSDETIE) { 533 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n"); 534 status = SNDRV_PCM_STATE_XRUN; 535 } 536 537 if (flags & SAI_XIMR_LFSDETIE) { 538 dev_err(&pdev->dev, "IRQ Late frame synchro\n"); 539 status = SNDRV_PCM_STATE_XRUN; 540 } 541 542 spin_lock(&sai->irq_lock); 543 if (status != SNDRV_PCM_STATE_RUNNING && sai->substream) 544 snd_pcm_stop_xrun(sai->substream); 545 spin_unlock(&sai->irq_lock); 546 547 return IRQ_HANDLED; 548} 549 550static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai, 551 int clk_id, unsigned int freq, int dir) 552{ 553 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 554 int ret; 555 556 if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) { 557 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 558 SAI_XCR1_NODIV, 559 freq ? 0 : SAI_XCR1_NODIV); 560 if (ret < 0) 561 return ret; 562 563 /* Assume shutdown if requested frequency is 0Hz */ 564 if (!freq) { 565 /* Release mclk rate only if rate was actually set */ 566 if (sai->mclk_rate) { 567 clk_rate_exclusive_put(sai->sai_mclk); 568 sai->mclk_rate = 0; 569 } 570 return 0; 571 } 572 573 /* If master clock is used, set parent clock now */ 574 ret = stm32_sai_set_parent_clock(sai, freq); 575 if (ret) 576 return ret; 577 578 ret = clk_set_rate_exclusive(sai->sai_mclk, freq); 579 if (ret) { 580 dev_err(cpu_dai->dev, 581 ret == -EBUSY ? 582 "Active streams have incompatible rates" : 583 "Could not set mclk rate\n"); 584 return ret; 585 } 586 587 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq); 588 sai->mclk_rate = freq; 589 } 590 591 return 0; 592} 593 594static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 595 u32 rx_mask, int slots, int slot_width) 596{ 597 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 598 int slotr, slotr_mask, slot_size; 599 600 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 601 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n"); 602 return 0; 603 } 604 605 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n", 606 tx_mask, rx_mask, slots, slot_width); 607 608 switch (slot_width) { 609 case 16: 610 slot_size = SAI_SLOT_SIZE_16; 611 break; 612 case 32: 613 slot_size = SAI_SLOT_SIZE_32; 614 break; 615 default: 616 slot_size = SAI_SLOT_SIZE_AUTO; 617 break; 618 } 619 620 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) | 621 SAI_XSLOTR_NBSLOT_SET(slots - 1); 622 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK; 623 624 /* tx/rx mask set in machine init, if slot number defined in DT */ 625 if (STM_SAI_IS_PLAYBACK(sai)) { 626 sai->slot_mask = tx_mask; 627 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask); 628 } 629 630 if (STM_SAI_IS_CAPTURE(sai)) { 631 sai->slot_mask = rx_mask; 632 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask); 633 } 634 635 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK; 636 637 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, slotr_mask, slotr); 638 639 sai->slot_width = slot_width; 640 sai->slots = slots; 641 642 return 0; 643} 644 645static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 646{ 647 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 648 int cr1, frcr = 0; 649 int cr1_mask, frcr_mask = 0; 650 int ret; 651 652 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); 653 654 /* Do not generate master by default */ 655 cr1 = SAI_XCR1_NODIV; 656 cr1_mask = SAI_XCR1_NODIV; 657 658 cr1_mask |= SAI_XCR1_PRTCFG_MASK; 659 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 660 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL); 661 goto conf_update; 662 } 663 664 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL); 665 666 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 667 /* SCK active high for all protocols */ 668 case SND_SOC_DAIFMT_I2S: 669 cr1 |= SAI_XCR1_CKSTR; 670 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF; 671 break; 672 /* Left justified */ 673 case SND_SOC_DAIFMT_MSB: 674 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 675 break; 676 /* Right justified */ 677 case SND_SOC_DAIFMT_LSB: 678 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 679 break; 680 case SND_SOC_DAIFMT_DSP_A: 681 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF; 682 break; 683 case SND_SOC_DAIFMT_DSP_B: 684 frcr |= SAI_XFRCR_FSPOL; 685 break; 686 default: 687 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", 688 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 689 return -EINVAL; 690 } 691 692 cr1_mask |= SAI_XCR1_CKSTR; 693 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF | 694 SAI_XFRCR_FSDEF; 695 696 /* DAI clock strobing. Invert setting previously set */ 697 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 698 case SND_SOC_DAIFMT_NB_NF: 699 break; 700 case SND_SOC_DAIFMT_IB_NF: 701 cr1 ^= SAI_XCR1_CKSTR; 702 break; 703 case SND_SOC_DAIFMT_NB_IF: 704 frcr ^= SAI_XFRCR_FSPOL; 705 break; 706 case SND_SOC_DAIFMT_IB_IF: 707 /* Invert fs & sck */ 708 cr1 ^= SAI_XCR1_CKSTR; 709 frcr ^= SAI_XFRCR_FSPOL; 710 break; 711 default: 712 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", 713 fmt & SND_SOC_DAIFMT_INV_MASK); 714 return -EINVAL; 715 } 716 cr1_mask |= SAI_XCR1_CKSTR; 717 frcr_mask |= SAI_XFRCR_FSPOL; 718 719 stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr); 720 721 /* DAI clock master masks */ 722 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 723 case SND_SOC_DAIFMT_CBM_CFM: 724 /* codec is master */ 725 cr1 |= SAI_XCR1_SLAVE; 726 sai->master = false; 727 break; 728 case SND_SOC_DAIFMT_CBS_CFS: 729 sai->master = true; 730 break; 731 default: 732 dev_err(cpu_dai->dev, "Unsupported mode %#x\n", 733 fmt & SND_SOC_DAIFMT_MASTER_MASK); 734 return -EINVAL; 735 } 736 737 /* Set slave mode if sub-block is synchronized with another SAI */ 738 if (sai->sync) { 739 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n"); 740 cr1 |= SAI_XCR1_SLAVE; 741 sai->master = false; 742 } 743 744 cr1_mask |= SAI_XCR1_SLAVE; 745 746conf_update: 747 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1); 748 if (ret < 0) { 749 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 750 return ret; 751 } 752 753 sai->fmt = fmt; 754 755 return 0; 756} 757 758static int stm32_sai_startup(struct snd_pcm_substream *substream, 759 struct snd_soc_dai *cpu_dai) 760{ 761 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 762 int imr, cr2, ret; 763 unsigned long flags; 764 765 spin_lock_irqsave(&sai->irq_lock, flags); 766 sai->substream = substream; 767 spin_unlock_irqrestore(&sai->irq_lock, flags); 768 769 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 770 snd_pcm_hw_constraint_mask64(substream->runtime, 771 SNDRV_PCM_HW_PARAM_FORMAT, 772 SNDRV_PCM_FMTBIT_S32_LE); 773 snd_pcm_hw_constraint_single(substream->runtime, 774 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 775 } 776 777 ret = clk_prepare_enable(sai->sai_ck); 778 if (ret < 0) { 779 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); 780 return ret; 781 } 782 783 /* Enable ITs */ 784 stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, 785 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK); 786 787 imr = SAI_XIMR_OVRUDRIE; 788 if (STM_SAI_IS_CAPTURE(sai)) { 789 stm32_sai_sub_reg_rd(sai, STM_SAI_CR2_REGX, &cr2); 790 if (cr2 & SAI_XCR2_MUTECNT_MASK) 791 imr |= SAI_XIMR_MUTEDETIE; 792 } 793 794 if (sai->master) 795 imr |= SAI_XIMR_WCKCFGIE; 796 else 797 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE; 798 799 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, 800 SAI_XIMR_MASK, imr); 801 802 return 0; 803} 804 805static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai, 806 struct snd_pcm_substream *substream, 807 struct snd_pcm_hw_params *params) 808{ 809 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 810 int cr1, cr1_mask, ret; 811 812 /* 813 * DMA bursts increment is set to 4 words. 814 * SAI fifo threshold is set to half fifo, to keep enough space 815 * for DMA incoming bursts. 816 */ 817 stm32_sai_sub_reg_wr(sai, STM_SAI_CR2_REGX, 818 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK, 819 SAI_XCR2_FFLUSH | 820 SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF)); 821 822 /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/ 823 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 824 sai->spdif_frm_cnt = 0; 825 return 0; 826 } 827 828 /* Mode, data format and channel config */ 829 cr1_mask = SAI_XCR1_DS_MASK; 830 switch (params_format(params)) { 831 case SNDRV_PCM_FORMAT_S8: 832 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8); 833 break; 834 case SNDRV_PCM_FORMAT_S16_LE: 835 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16); 836 break; 837 case SNDRV_PCM_FORMAT_S32_LE: 838 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32); 839 break; 840 default: 841 dev_err(cpu_dai->dev, "Data format not supported\n"); 842 return -EINVAL; 843 } 844 845 cr1_mask |= SAI_XCR1_MONO; 846 if ((sai->slots == 2) && (params_channels(params) == 1)) 847 cr1 |= SAI_XCR1_MONO; 848 849 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1); 850 if (ret < 0) { 851 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 852 return ret; 853 } 854 855 return 0; 856} 857 858static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai) 859{ 860 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 861 int slotr, slot_sz; 862 863 stm32_sai_sub_reg_rd(sai, STM_SAI_SLOTR_REGX, &slotr); 864 865 /* 866 * If SLOTSZ is set to auto in SLOTR, align slot width on data size 867 * By default slot width = data size, if not forced from DT 868 */ 869 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK; 870 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO)) 871 sai->slot_width = sai->data_size; 872 873 if (sai->slot_width < sai->data_size) { 874 dev_err(cpu_dai->dev, 875 "Data size %d larger than slot width\n", 876 sai->data_size); 877 return -EINVAL; 878 } 879 880 /* Slot number is set to 2, if not specified in DT */ 881 if (!sai->slots) 882 sai->slots = 2; 883 884 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/ 885 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, 886 SAI_XSLOTR_NBSLOT_MASK, 887 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); 888 889 /* Set default slots mask if not already set from DT */ 890 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) { 891 sai->slot_mask = (1 << sai->slots) - 1; 892 stm32_sai_sub_reg_up(sai, 893 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK, 894 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); 895 } 896 897 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n", 898 sai->slots, sai->slot_width); 899 900 return 0; 901} 902 903static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai) 904{ 905 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 906 int fs_active, offset, format; 907 int frcr, frcr_mask; 908 909 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK; 910 sai->fs_length = sai->slot_width * sai->slots; 911 912 fs_active = sai->fs_length / 2; 913 if ((format == SND_SOC_DAIFMT_DSP_A) || 914 (format == SND_SOC_DAIFMT_DSP_B)) 915 fs_active = 1; 916 917 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1)); 918 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1)); 919 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK; 920 921 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n", 922 sai->fs_length, fs_active); 923 924 stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr); 925 926 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { 927 offset = sai->slot_width - sai->data_size; 928 929 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, 930 SAI_XSLOTR_FBOFF_MASK, 931 SAI_XSLOTR_FBOFF_SET(offset)); 932 } 933} 934 935static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai) 936{ 937 unsigned char *cs = sai->iec958.status; 938 939 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; 940 cs[1] = IEC958_AES1_CON_GENERAL; 941 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; 942 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID; 943} 944 945static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai, 946 struct snd_pcm_runtime *runtime) 947{ 948 if (!runtime) 949 return; 950 951 /* Force the sample rate according to runtime rate */ 952 mutex_lock(&sai->ctrl_lock); 953 switch (runtime->rate) { 954 case 22050: 955 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050; 956 break; 957 case 44100: 958 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100; 959 break; 960 case 88200: 961 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200; 962 break; 963 case 176400: 964 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400; 965 break; 966 case 24000: 967 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000; 968 break; 969 case 48000: 970 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000; 971 break; 972 case 96000: 973 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000; 974 break; 975 case 192000: 976 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000; 977 break; 978 case 32000: 979 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000; 980 break; 981 default: 982 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID; 983 break; 984 } 985 mutex_unlock(&sai->ctrl_lock); 986} 987 988static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai, 989 struct snd_pcm_hw_params *params) 990{ 991 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 992 int div = 0, cr1 = 0; 993 int sai_clk_rate, mclk_ratio, den; 994 unsigned int rate = params_rate(params); 995 int ret; 996 997 if (!sai->sai_mclk) { 998 ret = stm32_sai_set_parent_clock(sai, rate); 999 if (ret) 1000 return ret; 1001 } 1002 sai_clk_rate = clk_get_rate(sai->sai_ck); 1003 1004 if (STM_SAI_IS_F4(sai->pdata)) { 1005 /* mclk on (NODIV=0) 1006 * mclk_rate = 256 * fs 1007 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate 1008 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise 1009 * mclk off (NODIV=1) 1010 * MCKDIV ignored. sck = sai_ck 1011 */ 1012 if (!sai->mclk_rate) 1013 return 0; 1014 1015 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) { 1016 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1017 2 * sai->mclk_rate); 1018 if (div < 0) 1019 return div; 1020 } 1021 } else { 1022 /* 1023 * TDM mode : 1024 * mclk on 1025 * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0) 1026 * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1) 1027 * mclk off 1028 * MCKDIV = sai_ck / (frl x ws) (NOMCK=1) 1029 * Note: NOMCK/NODIV correspond to same bit. 1030 */ 1031 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1032 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1033 rate * 128); 1034 if (div < 0) 1035 return div; 1036 } else { 1037 if (sai->mclk_rate) { 1038 mclk_ratio = sai->mclk_rate / rate; 1039 if (mclk_ratio == 512) { 1040 cr1 = SAI_XCR1_OSR; 1041 } else if (mclk_ratio != 256) { 1042 dev_err(cpu_dai->dev, 1043 "Wrong mclk ratio %d\n", 1044 mclk_ratio); 1045 return -EINVAL; 1046 } 1047 1048 stm32_sai_sub_reg_up(sai, 1049 STM_SAI_CR1_REGX, 1050 SAI_XCR1_OSR, cr1); 1051 1052 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1053 sai->mclk_rate); 1054 if (div < 0) 1055 return div; 1056 } else { 1057 /* mclk-fs not set, master clock not active */ 1058 den = sai->fs_length * params_rate(params); 1059 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1060 den); 1061 if (div < 0) 1062 return div; 1063 } 1064 } 1065 } 1066 1067 return stm32_sai_set_clk_div(sai, div); 1068} 1069 1070static int stm32_sai_hw_params(struct snd_pcm_substream *substream, 1071 struct snd_pcm_hw_params *params, 1072 struct snd_soc_dai *cpu_dai) 1073{ 1074 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1075 int ret; 1076 1077 sai->data_size = params_width(params); 1078 1079 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1080 /* Rate not already set in runtime structure */ 1081 substream->runtime->rate = params_rate(params); 1082 stm32_sai_set_iec958_status(sai, substream->runtime); 1083 } else { 1084 ret = stm32_sai_set_slots(cpu_dai); 1085 if (ret < 0) 1086 return ret; 1087 stm32_sai_set_frame(cpu_dai); 1088 } 1089 1090 ret = stm32_sai_set_config(cpu_dai, substream, params); 1091 if (ret) 1092 return ret; 1093 1094 if (sai->master) 1095 ret = stm32_sai_configure_clock(cpu_dai, params); 1096 1097 return ret; 1098} 1099 1100static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd, 1101 struct snd_soc_dai *cpu_dai) 1102{ 1103 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1104 int ret; 1105 1106 switch (cmd) { 1107 case SNDRV_PCM_TRIGGER_START: 1108 case SNDRV_PCM_TRIGGER_RESUME: 1109 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1110 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n"); 1111 1112 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1113 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN); 1114 1115 /* Enable SAI */ 1116 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1117 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN); 1118 if (ret < 0) 1119 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 1120 break; 1121 case SNDRV_PCM_TRIGGER_SUSPEND: 1122 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1123 case SNDRV_PCM_TRIGGER_STOP: 1124 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n"); 1125 1126 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, 1127 SAI_XIMR_MASK, 0); 1128 1129 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1130 SAI_XCR1_SAIEN, 1131 (unsigned int)~SAI_XCR1_SAIEN); 1132 1133 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1134 SAI_XCR1_DMAEN, 1135 (unsigned int)~SAI_XCR1_DMAEN); 1136 if (ret < 0) 1137 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 1138 1139 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1140 sai->spdif_frm_cnt = 0; 1141 break; 1142 default: 1143 return -EINVAL; 1144 } 1145 1146 return ret; 1147} 1148 1149static void stm32_sai_shutdown(struct snd_pcm_substream *substream, 1150 struct snd_soc_dai *cpu_dai) 1151{ 1152 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1153 unsigned long flags; 1154 1155 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0); 1156 1157 clk_disable_unprepare(sai->sai_ck); 1158 1159 spin_lock_irqsave(&sai->irq_lock, flags); 1160 sai->substream = NULL; 1161 spin_unlock_irqrestore(&sai->irq_lock, flags); 1162} 1163 1164static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd, 1165 struct snd_soc_dai *cpu_dai) 1166{ 1167 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1168 struct snd_kcontrol_new knew = iec958_ctls; 1169 1170 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1171 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__); 1172 knew.device = rtd->pcm->device; 1173 return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai)); 1174 } 1175 1176 return 0; 1177} 1178 1179static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai) 1180{ 1181 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1182 int cr1 = 0, cr1_mask, ret; 1183 1184 sai->cpu_dai = cpu_dai; 1185 1186 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX); 1187 /* 1188 * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice, 1189 * as it allows bytes, half-word and words transfers. (See DMA fifos 1190 * constraints). 1191 */ 1192 sai->dma_params.maxburst = 4; 1193 if (sai->pdata->conf.fifo_size < 8) 1194 sai->dma_params.maxburst = 1; 1195 /* Buswidth will be set by framework at runtime */ 1196 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 1197 1198 if (STM_SAI_IS_PLAYBACK(sai)) 1199 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL); 1200 else 1201 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params); 1202 1203 /* Next settings are not relevant for spdif mode */ 1204 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1205 return 0; 1206 1207 cr1_mask = SAI_XCR1_RX_TX; 1208 if (STM_SAI_IS_CAPTURE(sai)) 1209 cr1 |= SAI_XCR1_RX_TX; 1210 1211 /* Configure synchronization */ 1212 if (sai->sync == SAI_SYNC_EXTERNAL) { 1213 /* Configure synchro client and provider */ 1214 ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider, 1215 sai->synco, sai->synci); 1216 if (ret) 1217 return ret; 1218 } 1219 1220 cr1_mask |= SAI_XCR1_SYNCEN_MASK; 1221 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync); 1222 1223 return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1); 1224} 1225 1226static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = { 1227 .set_sysclk = stm32_sai_set_sysclk, 1228 .set_fmt = stm32_sai_set_dai_fmt, 1229 .set_tdm_slot = stm32_sai_set_dai_tdm_slot, 1230 .startup = stm32_sai_startup, 1231 .hw_params = stm32_sai_hw_params, 1232 .trigger = stm32_sai_trigger, 1233 .shutdown = stm32_sai_shutdown, 1234}; 1235 1236static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream, 1237 int channel, unsigned long hwoff, 1238 void *buf, unsigned long bytes) 1239{ 1240 struct snd_pcm_runtime *runtime = substream->runtime; 1241 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 1242 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); 1243 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1244 int *ptr = (int *)(runtime->dma_area + hwoff + 1245 channel * (runtime->dma_bytes / runtime->channels)); 1246 ssize_t cnt = bytes_to_samples(runtime, bytes); 1247 unsigned int frm_cnt = sai->spdif_frm_cnt; 1248 unsigned int byte; 1249 unsigned int mask; 1250 1251 do { 1252 *ptr = ((*ptr >> 8) & 0x00ffffff); 1253 1254 /* Set channel status bit */ 1255 byte = frm_cnt >> 3; 1256 mask = 1 << (frm_cnt - (byte << 3)); 1257 if (sai->iec958.status[byte] & mask) 1258 *ptr |= 0x04000000; 1259 ptr++; 1260 1261 if (!(cnt % 2)) 1262 frm_cnt++; 1263 1264 if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES) 1265 frm_cnt = 0; 1266 } while (--cnt); 1267 sai->spdif_frm_cnt = frm_cnt; 1268 1269 return 0; 1270} 1271 1272/* No support of mmap in S/PDIF mode */ 1273static const struct snd_pcm_hardware stm32_sai_pcm_hw_spdif = { 1274 .info = SNDRV_PCM_INFO_INTERLEAVED, 1275 .buffer_bytes_max = 8 * PAGE_SIZE, 1276 .period_bytes_min = 1024, 1277 .period_bytes_max = PAGE_SIZE, 1278 .periods_min = 2, 1279 .periods_max = 8, 1280}; 1281 1282static const struct snd_pcm_hardware stm32_sai_pcm_hw = { 1283 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 1284 .buffer_bytes_max = 8 * PAGE_SIZE, 1285 .period_bytes_min = 1024, /* 5ms at 48kHz */ 1286 .period_bytes_max = PAGE_SIZE, 1287 .periods_min = 2, 1288 .periods_max = 8, 1289}; 1290 1291static struct snd_soc_dai_driver stm32_sai_playback_dai = { 1292 .probe = stm32_sai_dai_probe, 1293 .pcm_new = stm32_sai_pcm_new, 1294 .id = 1, /* avoid call to fmt_single_name() */ 1295 .playback = { 1296 .channels_min = 1, 1297 .channels_max = 2, 1298 .rate_min = 8000, 1299 .rate_max = 192000, 1300 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1301 /* DMA does not support 24 bits transfers */ 1302 .formats = 1303 SNDRV_PCM_FMTBIT_S8 | 1304 SNDRV_PCM_FMTBIT_S16_LE | 1305 SNDRV_PCM_FMTBIT_S32_LE, 1306 }, 1307 .ops = &stm32_sai_pcm_dai_ops, 1308}; 1309 1310static struct snd_soc_dai_driver stm32_sai_capture_dai = { 1311 .probe = stm32_sai_dai_probe, 1312 .id = 1, /* avoid call to fmt_single_name() */ 1313 .capture = { 1314 .channels_min = 1, 1315 .channels_max = 2, 1316 .rate_min = 8000, 1317 .rate_max = 192000, 1318 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1319 /* DMA does not support 24 bits transfers */ 1320 .formats = 1321 SNDRV_PCM_FMTBIT_S8 | 1322 SNDRV_PCM_FMTBIT_S16_LE | 1323 SNDRV_PCM_FMTBIT_S32_LE, 1324 }, 1325 .ops = &stm32_sai_pcm_dai_ops, 1326}; 1327 1328static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = { 1329 .pcm_hardware = &stm32_sai_pcm_hw, 1330 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1331}; 1332 1333static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = { 1334 .pcm_hardware = &stm32_sai_pcm_hw_spdif, 1335 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1336 .process = stm32_sai_pcm_process_spdif, 1337}; 1338 1339static const struct snd_soc_component_driver stm32_component = { 1340 .name = "stm32-sai", 1341}; 1342 1343static const struct of_device_id stm32_sai_sub_ids[] = { 1344 { .compatible = "st,stm32-sai-sub-a", 1345 .data = (void *)STM_SAI_A_ID}, 1346 { .compatible = "st,stm32-sai-sub-b", 1347 .data = (void *)STM_SAI_B_ID}, 1348 {} 1349}; 1350MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids); 1351 1352static int stm32_sai_sub_parse_of(struct platform_device *pdev, 1353 struct stm32_sai_sub_data *sai) 1354{ 1355 struct device_node *np = pdev->dev.of_node; 1356 struct resource *res; 1357 void __iomem *base; 1358 struct of_phandle_args args; 1359 int ret; 1360 1361 if (!np) 1362 return -ENODEV; 1363 1364 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1365 base = devm_ioremap_resource(&pdev->dev, res); 1366 if (IS_ERR(base)) 1367 return PTR_ERR(base); 1368 1369 sai->phys_addr = res->start; 1370 1371 sai->regmap_config = &stm32_sai_sub_regmap_config_f4; 1372 /* Note: PDM registers not available for sub-block B */ 1373 if (STM_SAI_HAS_PDM(sai) && STM_SAI_IS_SUB_A(sai)) 1374 sai->regmap_config = &stm32_sai_sub_regmap_config_h7; 1375 1376 /* 1377 * Do not manage peripheral clock through regmap framework as this 1378 * can lead to circular locking issue with sai master clock provider. 1379 * Manage peripheral clock directly in driver instead. 1380 */ 1381 sai->regmap = devm_regmap_init_mmio(&pdev->dev, base, 1382 sai->regmap_config); 1383 if (IS_ERR(sai->regmap)) { 1384 if (PTR_ERR(sai->regmap) != -EPROBE_DEFER) 1385 dev_err(&pdev->dev, "Regmap init error %ld\n", 1386 PTR_ERR(sai->regmap)); 1387 return PTR_ERR(sai->regmap); 1388 } 1389 1390 /* Get direction property */ 1391 if (of_property_match_string(np, "dma-names", "tx") >= 0) { 1392 sai->dir = SNDRV_PCM_STREAM_PLAYBACK; 1393 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) { 1394 sai->dir = SNDRV_PCM_STREAM_CAPTURE; 1395 } else { 1396 dev_err(&pdev->dev, "Unsupported direction\n"); 1397 return -EINVAL; 1398 } 1399 1400 /* Get spdif iec60958 property */ 1401 sai->spdif = false; 1402 if (of_get_property(np, "st,iec60958", NULL)) { 1403 if (!STM_SAI_HAS_SPDIF(sai) || 1404 sai->dir == SNDRV_PCM_STREAM_CAPTURE) { 1405 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n"); 1406 return -EINVAL; 1407 } 1408 stm32_sai_init_iec958_status(sai); 1409 sai->spdif = true; 1410 sai->master = true; 1411 } 1412 1413 /* Get synchronization property */ 1414 args.np = NULL; 1415 ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args); 1416 if (ret < 0 && ret != -ENOENT) { 1417 dev_err(&pdev->dev, "Failed to get st,sync property\n"); 1418 return ret; 1419 } 1420 1421 sai->sync = SAI_SYNC_NONE; 1422 if (args.np) { 1423 if (args.np == np) { 1424 dev_err(&pdev->dev, "%pOFn sync own reference\n", np); 1425 of_node_put(args.np); 1426 return -EINVAL; 1427 } 1428 1429 sai->np_sync_provider = of_get_parent(args.np); 1430 if (!sai->np_sync_provider) { 1431 dev_err(&pdev->dev, "%pOFn parent node not found\n", 1432 np); 1433 of_node_put(args.np); 1434 return -ENODEV; 1435 } 1436 1437 sai->sync = SAI_SYNC_INTERNAL; 1438 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) { 1439 if (!STM_SAI_HAS_EXT_SYNC(sai)) { 1440 dev_err(&pdev->dev, 1441 "External synchro not supported\n"); 1442 of_node_put(args.np); 1443 return -EINVAL; 1444 } 1445 sai->sync = SAI_SYNC_EXTERNAL; 1446 1447 sai->synci = args.args[0]; 1448 if (sai->synci < 1 || 1449 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) { 1450 dev_err(&pdev->dev, "Wrong SAI index\n"); 1451 of_node_put(args.np); 1452 return -EINVAL; 1453 } 1454 1455 if (of_property_match_string(args.np, "compatible", 1456 "st,stm32-sai-sub-a") >= 0) 1457 sai->synco = STM_SAI_SYNC_OUT_A; 1458 1459 if (of_property_match_string(args.np, "compatible", 1460 "st,stm32-sai-sub-b") >= 0) 1461 sai->synco = STM_SAI_SYNC_OUT_B; 1462 1463 if (!sai->synco) { 1464 dev_err(&pdev->dev, "Unknown SAI sub-block\n"); 1465 of_node_put(args.np); 1466 return -EINVAL; 1467 } 1468 } 1469 1470 dev_dbg(&pdev->dev, "%s synchronized with %s\n", 1471 pdev->name, args.np->full_name); 1472 } 1473 1474 of_node_put(args.np); 1475 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck"); 1476 if (IS_ERR(sai->sai_ck)) { 1477 if (PTR_ERR(sai->sai_ck) != -EPROBE_DEFER) 1478 dev_err(&pdev->dev, "Missing kernel clock sai_ck: %ld\n", 1479 PTR_ERR(sai->sai_ck)); 1480 return PTR_ERR(sai->sai_ck); 1481 } 1482 1483 ret = clk_prepare(sai->pdata->pclk); 1484 if (ret < 0) 1485 return ret; 1486 1487 if (STM_SAI_IS_F4(sai->pdata)) 1488 return 0; 1489 1490 /* Register mclk provider if requested */ 1491 if (of_find_property(np, "#clock-cells", NULL)) { 1492 ret = stm32_sai_add_mclk_provider(sai); 1493 if (ret < 0) 1494 return ret; 1495 } else { 1496 sai->sai_mclk = devm_clk_get(&pdev->dev, "MCLK"); 1497 if (IS_ERR(sai->sai_mclk)) { 1498 if (PTR_ERR(sai->sai_mclk) != -ENOENT) 1499 return PTR_ERR(sai->sai_mclk); 1500 sai->sai_mclk = NULL; 1501 } 1502 } 1503 1504 return 0; 1505} 1506 1507static int stm32_sai_sub_probe(struct platform_device *pdev) 1508{ 1509 struct stm32_sai_sub_data *sai; 1510 const struct of_device_id *of_id; 1511 const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config; 1512 int ret; 1513 1514 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 1515 if (!sai) 1516 return -ENOMEM; 1517 1518 of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev); 1519 if (!of_id) 1520 return -EINVAL; 1521 sai->id = (uintptr_t)of_id->data; 1522 1523 sai->pdev = pdev; 1524 mutex_init(&sai->ctrl_lock); 1525 spin_lock_init(&sai->irq_lock); 1526 platform_set_drvdata(pdev, sai); 1527 1528 sai->pdata = dev_get_drvdata(pdev->dev.parent); 1529 if (!sai->pdata) { 1530 dev_err(&pdev->dev, "Parent device data not available\n"); 1531 return -EINVAL; 1532 } 1533 1534 ret = stm32_sai_sub_parse_of(pdev, sai); 1535 if (ret) 1536 return ret; 1537 1538 if (STM_SAI_IS_PLAYBACK(sai)) 1539 sai->cpu_dai_drv = stm32_sai_playback_dai; 1540 else 1541 sai->cpu_dai_drv = stm32_sai_capture_dai; 1542 sai->cpu_dai_drv.name = dev_name(&pdev->dev); 1543 1544 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr, 1545 IRQF_SHARED, dev_name(&pdev->dev), sai); 1546 if (ret) { 1547 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 1548 return ret; 1549 } 1550 1551 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1552 conf = &stm32_sai_pcm_config_spdif; 1553 1554 ret = snd_dmaengine_pcm_register(&pdev->dev, conf, 0); 1555 if (ret) { 1556 if (ret != -EPROBE_DEFER) 1557 dev_err(&pdev->dev, "Could not register pcm dma\n"); 1558 return ret; 1559 } 1560 1561 ret = snd_soc_register_component(&pdev->dev, &stm32_component, 1562 &sai->cpu_dai_drv, 1); 1563 if (ret) { 1564 snd_dmaengine_pcm_unregister(&pdev->dev); 1565 return ret; 1566 } 1567 1568 pm_runtime_enable(&pdev->dev); 1569 1570 return 0; 1571} 1572 1573static int stm32_sai_sub_remove(struct platform_device *pdev) 1574{ 1575 struct stm32_sai_sub_data *sai = dev_get_drvdata(&pdev->dev); 1576 1577 clk_unprepare(sai->pdata->pclk); 1578 snd_dmaengine_pcm_unregister(&pdev->dev); 1579 snd_soc_unregister_component(&pdev->dev); 1580 pm_runtime_disable(&pdev->dev); 1581 1582 return 0; 1583} 1584 1585#ifdef CONFIG_PM_SLEEP 1586static int stm32_sai_sub_suspend(struct device *dev) 1587{ 1588 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); 1589 int ret; 1590 1591 ret = clk_enable(sai->pdata->pclk); 1592 if (ret < 0) 1593 return ret; 1594 1595 regcache_cache_only(sai->regmap, true); 1596 regcache_mark_dirty(sai->regmap); 1597 1598 clk_disable(sai->pdata->pclk); 1599 1600 return 0; 1601} 1602 1603static int stm32_sai_sub_resume(struct device *dev) 1604{ 1605 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); 1606 int ret; 1607 1608 ret = clk_enable(sai->pdata->pclk); 1609 if (ret < 0) 1610 return ret; 1611 1612 regcache_cache_only(sai->regmap, false); 1613 ret = regcache_sync(sai->regmap); 1614 1615 clk_disable(sai->pdata->pclk); 1616 1617 return ret; 1618} 1619#endif /* CONFIG_PM_SLEEP */ 1620 1621static const struct dev_pm_ops stm32_sai_sub_pm_ops = { 1622 SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_sub_suspend, stm32_sai_sub_resume) 1623}; 1624 1625static struct platform_driver stm32_sai_sub_driver = { 1626 .driver = { 1627 .name = "st,stm32-sai-sub", 1628 .of_match_table = stm32_sai_sub_ids, 1629 .pm = &stm32_sai_sub_pm_ops, 1630 }, 1631 .probe = stm32_sai_sub_probe, 1632 .remove = stm32_sai_sub_remove, 1633}; 1634 1635module_platform_driver(stm32_sai_sub_driver); 1636 1637MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface"); 1638MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>"); 1639MODULE_ALIAS("platform:st,stm32-sai-sub"); 1640MODULE_LICENSE("GPL v2"); 1641